A period from when switching elements S1, S4 at first diagonal positions in a full-bridge inverter are turned off at the same time to when switching elements S2, S3 at second diagonal positions are turned on at the same time, is defined as T1, and a period from when the switching elements S2, S3 at the second diagonal positions are turned off at the same time to when the switching elements S1, S4 at the first diagonal positions are turned on at the same time, is defined as T2. With a total length of T1 and T2 set to be constant, the lengths of T1 and T2 are controlled to be changed every switching cycle.

A period from when switching elements S1, S4 at first diagonal positions in a full-bridge inverter are turned off at the same time to when switching elements S2, S3 at second diagonal positions are turned on at the same time, is defined as T1, and a period from when the switching elements S2, S3 at the second diagonal positions are turned off at the same time to when the switching elements S1, S4 at the first diagonal positions are turned on at the same time, is defined as T2. With a total length of T1 and T2 set to be constant, the lengths of T1 and T2 are controlled to be changed every switching cycle.

A power noise filter and a supply modulator including the same, and a wireless communication device including the power noise filter are provided. The power noise filter includes a band stop filter and a low pass filter. The band stop filter includes an inductor and a first capacitor, which are connected in parallel between first and second nodes. The first node receives a first voltage, which is filtered by the band pass filter to thereby generate a second voltage at the second node. The first low pass filter includes the inductor and a second capacitor, which has one end connected to the second node and an opposite end connected to a ground source.

A power noise filter and a supply modulator including the same, and a wireless communication device including the power noise filter are provided. The power noise filter includes a band stop filter and a low pass filter. The band stop filter includes an inductor and a first capacitor, which are connected in parallel between first and second nodes. The first node receives a first voltage, which is filtered by the band pass filter to thereby generate a second voltage at the second node. The first low pass filter includes the inductor and a second capacitor, which has one end connected to the second node and an opposite end connected to a ground source.

To provide a controller for power conversion circuit which can maintain the detection value of second voltage at the target value of second voltage without depending on feedback control, when the first voltage is varied. A controller for power conversion circuit changes a control value by feedback control so that the detection value of second voltage approaches a target value of second voltage; calculates a control value for control, by correcting the control value based on the detection value of first voltage so as to correct, in feedforward manner, a change of the control value due to a change of the first voltage if correction of the control value is not performed; and controls on/off the switching device based on the control value for control.

To provide a controller for power conversion circuit which can maintain the detection value of second voltage at the target value of second voltage without depending on feedback control, when the first voltage is varied. A controller for power conversion circuit changes a control value by feedback control so that the detection value of second voltage approaches a target value of second voltage; calculates a control value for control, by correcting the control value based on the detection value of first voltage so as to correct, in feedforward manner, a change of the control value due to a change of the first voltage if correction of the control value is not performed; and controls on/off the switching device based on the control value for control.

A master converter and a plurality of slave converters each have an input connected to an associated one of a plurality of power storage elements, respectively, and an output connected to an output terminal in parallel. The master converter converts the voltage of the associated capacitor based on a duty ratio for matching an output voltage to a voltage command value, outputs the converted voltage to the output terminal, and transmits a control signal indicative of the duty ratio to the plurality of slave converters via a signal insulation unit. Each of the plurality of slave converters converts the voltage of the associated capacitor in response to the control signal transmitted via the signal insulation unit and outputs the converted voltage to the output terminal. A correction means is configured to correct at least the duty ratio in the master converter such that the duty ratio in the master converter matches the duty ratio in each of the plurality of slave converters.

A driver circuit controls a half-bridge that includes a high-side power switch and a low-side power switch. The driver circuit may comprise a high-side compare unit configured to determine a first drain-to-source voltage, wherein the first drain-to-source voltage is associated with the high-side power switch when the high-side power switch is ON, and a low-side compare unit configured to determine a second drain-to-source voltage, wherein the second drain-to-source voltage is associated with the low-side power switch when the low-side power switch is ON. The high-side compare unit may be further configured to determine a third drain-to-source voltage, wherein the third drain-to-source voltage is associated with the high-side power switch when the high-side power switch is OFF, and the low-side compare unit may be further configured to determine a fourth drain-to-source voltage, wherein the fourth drain-to-source voltage is associated with the low-side power switch when the low-side power switch is OFF.

A driver circuit controls a half-bridge that includes a high-side power switch and a low-side power switch. The driver circuit may comprise a high-side compare unit configured to determine a first drain-to-source voltage, wherein the first drain-to-source voltage is associated with the high-side power switch when the high-side power switch is ON, and a low-side compare unit configured to determine a second drain-to-source voltage, wherein the second drain-to-source voltage is associated with the low-side power switch when the low-side power switch is ON. The high-side compare unit may be further configured to determine a third drain-to-source voltage, wherein the third drain-to-source voltage is associated with the high-side power switch when the high-side power switch is OFF, and the low-side compare unit may be further configured to determine a fourth drain-to-source voltage, wherein the fourth drain-to-source voltage is associated with the low-side power switch when the low-side power switch is OFF.

A semiconductor integrated circuit for power supply forming a power supply device generates an output voltage from an input voltage. The semiconductor integrated circuit includes a plurality of external terminals including a target external terminal; a target transistor disposed between the target external terminal and a reference conductive part having a predetermined reference potential; an output voltage monitoring circuit arranged to turn on or off the target transistor in accordance with the output voltage; and a constant current circuit arranged to supply a constant current to a point of the reference potential via the target external terminal.