An inrush current suppression device is an inrush current suppression device that suppresses an inrush current flowing from a DC power supply through a mechanical switch, and includes: a first capacitor having one end connected to a positive terminal of the DC power supply through the mechanical switch; a semiconductor switching element connected to the other end of the first capacitor and a negative terminal of DC power supply between the other end of the first capacitor and the negative terminal of the DC power supply; a resistance element connected in parallel to the semiconductor switching element; and a control circuit for controlling the semiconductor switching element. The control circuit has a first output port, and controls ON time and OFF time of the semiconductor switching element by outputting a PWM signal from the first output port to the semiconductor switching element after the mechanical switch is closed.

An inrush current suppression device is an inrush current suppression device that suppresses an inrush current flowing from a DC power supply through a mechanical switch, and includes: a first capacitor having one end connected to a positive terminal of the DC power supply through the mechanical switch; a semiconductor switching element connected to the other end of the first capacitor and a negative terminal of DC power supply between the other end of the first capacitor and the negative terminal of the DC power supply; a resistance element connected in parallel to the semiconductor switching element; and a control circuit for controlling the semiconductor switching element. The control circuit has a first output port, and controls ON time and OFF time of the semiconductor switching element by outputting a PWM signal from the first output port to the semiconductor switching element after the mechanical switch is closed.

This power supply unit of a control system outputs a notification signal to a calculation unit when a time in which an input voltage becomes smaller than a threshold voltage exceeds a prescribed first measurement time. When detecting that a predetermined second measurement time has elapsed after the notification signal has been received, the calculation unit outputs an instruction signal instructing the execution of a process before a stop in preparation for a prescribed stop of power supply, and executes the process before the stop in place of the current process. Settings of the threshold voltage and the second measurement time are configured to be changeable by means of an external operation.

This power supply unit of a control system outputs a notification signal to a calculation unit when a time in which an input voltage becomes smaller than a threshold voltage exceeds a prescribed first measurement time. When detecting that a predetermined second measurement time has elapsed after the notification signal has been received, the calculation unit outputs an instruction signal instructing the execution of a process before a stop in preparation for a prescribed stop of power supply, and executes the process before the stop in place of the current process. Settings of the threshold voltage and the second measurement time are configured to be changeable by means of an external operation.

An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may use a clock signal at a given frequency to output corresponding alternating current signals at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulating signal. The dithered clock signal may have at least three different frequency levels during a repeated cycle of the modulating signal. The at least three different frequency levels may include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency. The dithered clock signal may be, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.

An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may use a clock signal at a given frequency to output corresponding alternating current signals at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulating signal. The dithered clock signal may have at least three different frequency levels during a repeated cycle of the modulating signal. The at least three different frequency levels may include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency. The dithered clock signal may be, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.

An inrush current suppression device is an inrush current suppression device that suppresses an inrush current flowing from a DC power supply through a mechanical switch, and includes: a first capacitor having one end connected to a positive terminal of the DC power supply through the mechanical switch; a semiconductor switching element connected to the other end of the first capacitor and a negative terminal of DC power supply between the other end of the first capacitor and the negative terminal of the DC power supply; a resistance element connected in parallel to the semiconductor switching element; and a control circuit for controlling the semiconductor switching element. The control circuit has a first output port, and controls ON time and OFF time of the semiconductor switching element by outputting a PWM signal from the first output port to the semiconductor switching element after the mechanical switch is closed.

An inrush current suppression device is an inrush current suppression device that suppresses an inrush current flowing from a DC power supply through a mechanical switch, and includes: a first capacitor having one end connected to a positive terminal of the DC power supply through the mechanical switch; a semiconductor switching element connected to the other end of the first capacitor and a negative terminal of DC power supply between the other end of the first capacitor and the negative terminal of the DC power supply; a resistance element connected in parallel to the semiconductor switching element; and a control circuit for controlling the semiconductor switching element. The control circuit has a first output port, and controls ON time and OFF time of the semiconductor switching element by outputting a PWM signal from the first output port to the semiconductor switching element after the mechanical switch is closed.

This power supply unit of a control system outputs a notification signal to a calculation unit when a time in which an input voltage becomes smaller than a threshold voltage exceeds a prescribed first measurement time. When detecting that a predetermined second measurement time has elapsed after the notification signal has been received, the calculation unit outputs an instruction signal instructing the execution of a process before a stop in preparation for a prescribed stop of power supply, and executes the process before the stop in place of the current process. Settings of the threshold voltage and the second measurement time are configured to be changeable by means of an external operation.

An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may use a clock signal at a given frequency to output corresponding alternating current signals at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulating signal. The dithered clock signal may have at least three different frequency levels during a repeated cycle of the modulating signal. The at least three different frequency levels may include a fundamental frequency, a first frequency that is lower than the fundamental frequency, and a second frequency that is higher than the fundamental frequency. The dithered clock signal may be, during the repeated cycle of the modulating signal, at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency.