This frequency tripler system uses a cascade of integrated transistor circuit differential limiting amplifiers and tunable notch filters that can directly serve one or more outputs, such as a direct clock or local oscillator drive. With this topology, filtering is distributed between two or more stages of differential limiting amplifiers and tunable notch filters. This enables suppression of smaller fundamental tone by the differential limiting amplifiers along with the tunable notch filters and yields a strong third harmonic signal to directly drive high performance mixers and digital-to-analog converters.

This frequency tripler system uses a cascade of integrated transistor circuit differential limiting amplifiers and tunable notch filters that can directly serve one or more outputs, such as a direct clock or local oscillator drive. With this topology, filtering is distributed between two or more stages of differential limiting amplifiers and tunable notch filters. This enables suppression of smaller fundamental tone by the differential limiting amplifiers along with the tunable notch filters and yields a strong third harmonic signal to directly drive high performance mixers and digital-to-analog converters.

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4.sup.th-Generation (4G) communication system such as long-term evolution (LTE). According to various embodiments of the present disclosure, an apparatus of a transmitter in a wireless communication system may include an oscillating circuit for providing an oscillating signal, and a radio frequency (RF) circuit for converting a frequency of a transmit signal using the oscillating signal, and transmitting the transmit signal. The oscillating circuit may generate a base oscillating signal of a differential signal form, by multiplying a first signal and a second signal which constitute the different signal, generate a first signal set from the first signal and a second signal set from the second signal, and generate a signal in which at least one harmonic component adjacent to an intended frequency component is suppressed using the first signal set and the second signal set.

A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler.

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4.sup.th-Generation (4G) communication system such as long-term evolution (LTE). According to various embodiments of the present disclosure, an apparatus of a transmitter in a wireless communication system may include an oscillating circuit for providing an oscillating signal, and a radio frequency (RF) circuit for converting a frequency of a transmit signal using the oscillating signal, and transmitting the transmit signal. The oscillating circuit may generate a base oscillating signal of a differential signal form, by multiplying a first signal and a second signal which constitute the different signal, generate a first signal set from the first signal and a second signal set from the second signal, and generate a signal in which at least one harmonic component adjacent to an intended frequency component is suppressed using the first signal set and the second signal set.

A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler.

A pulse generator is disclosed. The pulse generator can include a pulsed switch, such as a diode. The pulsed switched can be connected between an input source, such as an oscillator and a frequency multiplier.

A pulse generator is disclosed. The pulse generator can include a pulsed switch, such as a diode. The pulsed switched can be connected between an input source, such as an oscillator and a frequency multiplier.

A pulse generator is disclosed. The pulse generator can include a pulsed switch, such as a diode. The pulsed switched can be connected between an input source, such as an oscillator and a frequency multiplier.

A pulse generator is disclosed. The pulse generator can include a pulsed switch, such as a diode. The pulsed switched can be connected between an input source, such as an oscillator and a frequency multiplier.