An oscillating device includes a first quartz crystal resonator, a driving circuit, a first waveform adjustment circuit, and at least two second quartz crystal resonators. The first quartz crystal resonator has a first resonant frequency. The driving circuit, coupled to the first quartz crystal resonator, drives the first quartz crystal resonator to generate a first oscillating signal having the first resonant frequency. The second quartz crystal resonators, coupled in parallel and coupled to the driving circuit and the first quartz crystal resonator, have a second resonant frequency and receive and rectify the first oscillating signal to generate a second oscillating signal having the second resonant frequency. The first waveform adjustment circuit, coupled to the second quartz crystal resonators, receives the second oscillating signal and adjusts the second oscillating signal to generate a first waveform adjustment signal.

An analog computing system with coupled non-linear oscillators can solve complex combinatorial optimization problems using the weighted Ising model. The system is composed of a fully-connected LC oscillator network with low-cost electronic components and compatible with traditional integrated circuit technologies. Each LC oscillator, or node, in the network can be coupled to each other node in the array with a multiply and accumulate crossbar array or optical interconnects. When implemented with four nodes, the system performs with single-run ground state accuracies of 98% on randomized MAX-CUT problem sets with binary weights and 84% with five-bit weight resolutions. The four-node system can obtain solutions within five oscillator cycles with a time-to-solution that scales directly with oscillator frequency. A scaling analysis suggests that larger coupled oscillator networks may be used to solve computationally intensive problems faster and more efficiently than conventional algorithms.

An oscillating device includes a first quartz crystal resonator, a driving circuit, a first waveform adjustment circuit, and at least two second quartz crystal resonators. The first quartz crystal resonator has a first resonant frequency. The driving circuit, coupled to the first quartz crystal resonator, drives the first quartz crystal resonator to generate a first oscillating signal having the first resonant frequency. The second quartz crystal resonators, coupled in parallel and coupled to the driving circuit and the first quartz crystal resonator, have a second resonant frequency and receive and rectify the first oscillating signal to generate a second oscillating signal having the second resonant frequency. The first waveform adjustment circuit, coupled to the second quartz crystal resonators, receives the second oscillating signal and adjusts the second oscillating signal to generate a first waveform adjustment signal.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.

Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.

A circuit includes a first digital controlled oscillator and a second digital controlled oscillator coupled to the first digital controlled oscillator. A skew detector is connected to determine a skew between outputs of the first digital controlled oscillator and the second digital controlled oscillator, and a decoder is utilized to output a control signal, based on the skew, to modify a frequency of the first digital controlled oscillator using a switched capacitor array to reduce or eliminate the skew. A differential pulse injection oscillator circuit and a pulse injection signal generator circuit are also provided,

In some embodiments, there is provided an apparatus including a common bus and a plurality of oscillatrode circuits coupled to the common bus, the plurality of oscillatrode circuits including a first oscillatrode circuit outputting a first frequency tone when a first input voltage is detected by the first oscillatrode circuit and a second oscillatrode circuit outputting a second frequency tone when a second input voltage is detected by the second oscillatrode circuit, wherein common bus carries the first frequency tone and the second frequency tone at different frequencies in a frequency division multiplex signal. Related systems, methods, and articles of manufacture are also disclosed.