A polar transmitter provided for transmitting a phase/frequency modulated and amplitude modulated transmit signal and a method for generating a transmit signal using a polar transmitter are described. An example polar transmitter comprises a phase locked loop for generating a phase/frequency modulated precursor of the transmit signal. The phase locked loop comprises at its input a phase error detection unit for detecting a phase error of the precursor fed back from the output of the phase locked loop to the phase error detection unit as a feedback signal. The polar transmitter comprises a digital amplitude modulator for amplitude modulation of the precursor, resulting in the transmit signal. The digital amplitude modulator is arranged within the phase locked loop for amplitude modulation of the precursor before being output by the PLL. The phase error detection unit is further provided for detecting the amplitude of the feedback signal.

In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. Each level shifter is configured to output a corresponding phase clock signal of the first set of phase clock signals. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to at least one of a first or second phase clock signal of the first set of phase clock signals or a set of control signals. The first clock output signal has a second duty cycle. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.

Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

An example phase-locked loop (PLL) includes a digital filter, an oscillator, and a time-to-digital converter (TDC). The digital filter is configured to sample at a discrete time that is responsive to a reference clock signal received at the digital filter. The oscillator is coupled to the digital filter and configured to generate an output signal of the PLL. The TDC is coupled to the oscillator to determine a phase difference between the output signal and the reference clock signal. The TDC also provides a time signal to the digital filter that is based on the phase difference and is representative of an instantaneous rate of operation of the PLL. The digital filter is further configured to adjust a response characteristic of the digital filter according to the time signal.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

A circuit device includes a comparator, a reference voltage generation circuit, and a coupling control circuit. The comparator is configured to output a power-on reset signal by comparing a monitoring target voltage generated from a power supply voltage with a reference voltage. The reference voltage generation circuit is configured to generate the reference voltage. The coupling control circuit is coupled between a power supply voltage node and a reference voltage node. The coupling control circuit couples the reference voltage node and the power supply voltage node in a predetermined period after the power supply voltage is supplied.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a multiplexed selection signal, the first clock output signal having a second duty cycle; and adjust the second duty cycle responsive to at least a set of control signals or a phase difference between a first and second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.