A clock signal generating apparatus detects a phase difference between an input reference clock signal and a feedback signal to output a control signal based on the phase difference, generates the clock signal with a frequency based on the output control signal, generates a pattern by switching, at a certain time interval, between a plurality of patterns of a second phase shift amount, adds a first phase shift amount to the second phase shift amount having the generated pattern, determines a phase to be selected, so that a cycle of the phase-shifted clock signal matches the cycle of a clock signal changed by the first phase shift amount to which the second phase shift amount is added, selects the determined phase from among a plurality of phases, and generates a phase-shifted clock signal whose signal level changes in the selected phase for output as the feedback signal.

The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.

Systems, methods, and circuitries are provided for generating timing signals with a resonator-based open-loop oscillator circuitry. In one example, a system that generates a timing signal based on a target signal includes a plurality of oscillator units configured to generate a respective plurality of oscillator signals. Each oscillator unit includes a resonator that operates in an open-loop mode to generate a resonator signal having a resonator frequency. The resonator signal is used by core circuitry to generate a respective oscillator signal having a respective oscillator frequency. The resonator frequencies of the resonators in the plurality of oscillator units are different from one another. The system also includes a selector circuitry configured to select one of the plurality of oscillator units based on the target signal and provide a selected oscillator signal generated by the selected oscillator unit as the timing signal.

Systems, methods, and circuitries are provided for generating timing signals with a resonator-based open-loop oscillator circuitry. In one example, a system that generates a timing signal based on a target signal includes a plurality of oscillator units configured to generate a respective plurality of oscillator signals. Each oscillator unit includes a resonator that operates in an open-loop mode to generate a resonator signal having a resonator frequency. The resonator signal is used by core circuitry to generate a respective oscillator signal having a respective oscillator frequency. The resonator frequencies of the resonators in the plurality of oscillator units are different from one another. The system also includes a selector circuitry configured to select one of the plurality of oscillator units based on the target signal and provide a selected oscillator signal generated by the selected oscillator unit as the timing signal.

A wireless communication device includes a receiver circuit, a phase shift control circuit, and a digital phase-locked loop (DPLL) circuit. The receiver circuit includes a down-converter circuit that is used to apply down-conversion to an input signal according to a local oscillator (LO) signal. The phase shift control circuit is used to generate a phase shift signal. The DPLL circuit is used to generate the LO signal locked to an initial frequency under a frequency-lock state. In response to the phase shift signal, the DPLL circuit is further used to make the LO signal have a different frequency without leaving the frequency-lock state.

Interfaces between clock domains of an integrated circuit (IC) depend on synchronization of phase-locked loops (PLLs) that generate clocks in the different domains and on how each PLL responds to jitter in a shared reference clock. The well-controlled same bandwidth (and loop dynamic) for those PLLs renders the same and, therefore, ignorable reference jitter contribution. As a key component that determines a digital PLL bandwidth, digitally controlled oscillator (DCO) may have its gain vary with process, temperature, and supply IR drop from chip to chip or even module to module. A calibration circuit provides a gain correction factor to achieve a nominal gain in DCO as well as a desired/target PLL loop bandwidth. In some examples, the calibration circuit in each PLL determines a gain correction factor that causes the PLLs to have a common jitter response and stores the gain correction factors in the calibration circuits.

The method for calibrating the frequency synthesizer using two-point FSK modulation consists, in a first phase, in supplying an excitation signal generated by a calibration unit to a sigma-delta modulator by deactivating a digital-to-analog converter and transmitting the output signal from a loop filter of the synthesizer to the calibration unit, which digitally converts the incoming signal and offsets the phase shift between the excitation signal and the loop filter output signal in the calibration unit. In a second phase, the excitation signal is supplied to the sigma-delta modulator and to the activated digital-to-analog converter, and the digital-to-analog converter gain is calibrated by checking, in the calibration unit, the polarity of the loop filter output signal with respect to the excitation signal, and using a dichotomy algorithm.

A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.

A two-point phase modulator comprising a phase locked loop, PLL, having a voltage controlled oscillator, VCO, and a feedback path, a first modulation circuit for introducing a first modulation signal into the feedback path, the first modulation circuit generating the first modulation signal using a reference clock signal extracted from the PLL and derived from a first clock, a second modulation circuit for introducing a second modulation input into the VCO, the second modulation circuit generating the second modulation signal using a clock signal generated independently of the reference clock and a synchronizer for aligning the second modulation signal in time with the first clock signal.