H03D1/06

Electronic envelope detection circuit and corresponding demodulator
10951168 · 2021-03-16 · ·

An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Systems and methods for detecting local oscillator leakage and image tone in I/Q mixer based transceivers

A detector circuit includes: a squaring circuit configured to receive an output of a power amplifier of a radio transmitter and to produce an output current, the output of the power amplifier including: a desired tone; a local oscillator leakage tone; and an image tone, and the output current of the squaring circuit including: a direct current (DC) component including a function of the desired tone and an alternating current (AC) component; and a DC current absorber electrically connected to an output terminal of the squaring circuit, the DC current absorber being configured to filter out the DC component of the output current of the squaring circuit to produce a filtered output of the squaring circuit, the filtered output including the AC component including functions of the local oscillator leakage tone and the image tone.

ELECTRONIC ENVELOPE DETECTION CIRCUIT AND CORRESPONDING DEMODULATOR
20200228061 · 2020-07-16 · ·

An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

ELECTRONIC ENVELOPE DETECTION CIRCUIT AND CORRESPONDING DEMODULATOR
20200228061 · 2020-07-16 · ·

An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Distortion cancellation

The present disclosure provides for distortion cancelled by receiving a collided signal comprising first and second signals carrying respective first and second packets; digitizing the collided signal into a first digital signal and decoding the first packet therefrom; calculating a digital linear interference component of the first packet on the second from an estimated signal re-encoding the decoded first packet; synthesizing an analog linear interference component from the digital linear interference component; determining a digital nonlinear interference component of the first packet on the second from the first digital signal; amplifying the collided signal to produce a second amplified signal; removing the analog linear interference component from the second amplified signal to produce a partially de-interfered signal; removing the digital nonlinear interference component from the partially de-interfered signal to produce a de-interfered signal; and decoding the second packet from the de-interfered signal.

Timing estimation device and timing estimation method

A timing estimation device according to the present invention includes a received signal memory that outputs a plurality of sample groups each of which is a first number of samples extracted at symbol rate intervals from an oversampled received signal containing a known sequence, with shifting their leading positions by one sample from each other, a reliability calculation unit that calculates a channel impulse response for each of the sample groups, based on the sample group, generates a replica of the received signal using the channel impulse response and the known sequence, and calculates a reliability value based on the sample group, the replica, and the channel impulse response, and a timing estimation unit that estimates a preceding wave arrival timing and a delayed wave arrival timing, based on the reliability value.

Configuration and management of an active set

There is provided a method comprising: determining an information on an inter-symbol interference between signals on a same frequency resource and a same time resource from one or more first cells and one or more second cells, wherein an active set of the apparatus comprises at least the one or more second cells, the inter-symbol interference is an estimated inter-symbol interference if at least one of the one or more first cells is not in the active set, and the inter-symbol interference is a measured inter-symbol interference if the active set consists of the one or more first cells and the one or more second cells; and deciding whether or not to inform a network comprising the one or more first cells and the one or more second cells on the information on the inter-symbol interference.

Current-mode filtering using current steering

An apparatus is disclosed for current-mode filtering using current steering. In an example aspect, the apparatus includes a filter. The filter includes a current-steering node, a first output node, a second output node, a wideband path, and a narrowband path. The wideband path is coupled between the current-steering node and the first output node. The wideband path includes a wideband low-pass filter configured to pass frequencies within a wide passband. The narrowband path is coupled between the current-steering node and the second output node. The narrowband path includes a narrowband low-pass filter configured to pass a portion of the frequencies that are within a narrow passband.

Distortion cancellation

The present disclosure provides for distortion cancelled by receiving a collided signal, the collided signal comprising a first signal carrying a first packet and a second signal carrying a second packet; amplifying and digitizing the collided signal into a first digital signal at a first gain and a second digital signal at a second gain that is greater than the first gain; determining a nonlinear interference component of the first packet on the second packet from the first digital signal; decoding the first packet from the first digital signal; re-encoding the first packet with a first estimated channel effect into an estimated signal; calculating a linear interference component of the first packet on the second packet from the estimated signal; removing the linear interference component and the nonlinear interference component from the second digital signal to produce a de-interfered signal; and decoding the second packet from the de-interfered signal.

Beamspace nonlinear equalization for spur reduction
10536302 · 2020-01-14 · ·

System and method for beamspace nonlinear equalization in a plurality of parallel channels includes: receiving M parallel signals for transmission by N channels, respectively, wherein M is an integer greater than or equal to 1 and N is an integer greater than 1; performing a linear transfer function on each of the M parallel signal by a finite impulse response (FIR) filter; adding FIR filter tap outputs to each M parallel signals, respectively; phase shifting an output of a respective FIR filter per each of the M parallel signals to generate M intermediate channelized output signals per each of the N channels; summing, by a single summer, the M intermediate channelized output signals across the N channels to produce M channelized polyphase output signals; serializing the M channelized polyphase output signals to generate serialized M polyphase output signals; and equalizing the serialized M polyphase output signals to produce a linearized signal in beamspace.