A demodulator including a peak sampler to control an ADC or a digital resampler to sample a carrier signal in an unmodulated state at peaks, and to sample the carrier signal in a modulated state at a phase of the unmodulated state; and an envelope builder to determine an envelope signal based on differentials between maximum and minimum peaks of respective cycles of the sampled carrier signal. Further, a demodulator having an offset estimator to estimate in-phase and quadrature components of a carrier signal in an unmodulated state to determine in-phase and quadrature component offsets; a load modulated signal estimator to estimate in-phase and quadrature components of a load modulated signal by removing the in-phase and quadrature component offsets from in-phase and quadrature component samples of the carrier signal; and an envelope builder to build an envelope signal by combining the in-phase and quadrature components of the load modulated signal.

A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.

A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.

A demodulator including a peak sampler to control an ADC or a digital resampler to sample a carrier signal in an unmodulated state at peaks, and to sample the carrier signal in a modulated state at a phase of the unmodulated state; and an envelope builder to determine an envelope signal based on differentials between maximum and minimum peaks of respective cycles of the sampled carrier signal. Further, a demodulator having an offset estimator to estimate in-phase and quadrature components of a carrier signal in an unmodulated state to determine in-phase and quadrature component offsets; a load modulated signal estimator to estimate in-phase and quadrature components of a load modulated signal by removing the in-phase and quadrature component offsets from in-phase and quadrature component samples of the carrier signal; and an envelope builder to build an envelope signal by combining the in-phase and quadrature components of the load modulated signal.

In a digital envelope detector circuit, an input terminal receives a digital input signal and an output terminal produces a digital output signal. First and second digital processing circuitry between the input and output terminals each includes a memory element. The first processing circuitry applies low-pass filtering to the digital input signal. The second processing circuitry processes the digital input signal, stores in the memory element a value indicative of the processed digital input signal, and processes the output from the memory element so that the digital input signal is passed unaltered. A digital comparator circuit compares the digital input and output signals, asserts a control signal in response to the digital input signal being higher, and de-asserts the control signal in response to the digital input signal being lower. The first/second processing circuitry produces the digital output signal in response to the control signal being de-asserted/asserted.