An electronic device may include a harmonic rejection mixer with a delay line, mixer array, and load. The delay line may generate LO phases. Each mixer in the array may have a first input that receives an LO phase and a second input coupled to an input switch and the first input of the next mixer circuit through an inter-mixer switch. The load may include a set of switches. In a transmit mode, the input switches and set of switches may be closed while the inter-mixer switches are open. In a self-calibration mode, the input switches and set of switches may be open while the inter-mixer switches are closed. A controller may sweep through phase codes for the programmable delay line while storing a digital output from the load. The controller may calibrate the phase code based on the digital output.

A down-conversion mixer includes a converting-and-mixing circuit and a load circuit. The converting-and-mixing circuit performs voltage to current conversion and mixing with a differential oscillatory voltage signal pair upon a differential input voltage signal pair to generate a differential mixed current signal pair. The load circuit includes two transistors each having a transconductance that varies according to a control voltage, two resistors each decreasing a threshold voltage of a respective one of the transistors, and a resistor-inductor circuit cooperating with the transistors to convert the differential mixed current signal pair into a differential mixed voltage signal pair.

A processor may calibrate a first actuator electrically coupled to a transconductance stage of the frequency conversion circuit. The transconductance stage may be configured to receive a differential signal input. Calibrating a first actuator may adjust a first basis vector associated with a differential direct current (DC) output of the transconductance stage. A processor may calibrate a second actuator electrically coupled to receive the differential current output of the transconductance stage and electrically coupled to a set of commutating devices of the frequency conversion circuit. The commutating devices may be configured to receive differential LO inputs. Calibrating a second actuator may adjust a second basis vector associated with a differential impedance of the set of commutating devices. A processor may offset responsive to adjusting the first basis vector and the second basis vector, the first leakage basis vector and second leakage basis vector of the LO leakage signal.

A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

An active mixer for frequency conversion used in a wireless communication system improves conversion gain and noise figure by improving switching characteristics of a mixer using a LO signal without requiring additional power consumption of an active mixer block. Further disclosed is a method for improving conversion gain and noise figure of an active mixer. The active mixer includes a switching stage for receiving a LO signal and selectively performing a switching-on/off operation for frequency conversion, a body signal generator for generating a body signal to be applied to a body of an NMOS transistor of the switching stage based on the LO signal, and a voltage controller for controlling the body signal generator to selectively apply the body signal to the body of the NMOS transistor based on to the switching-on/off operation of the switching stage to control a threshold voltage of the transistor of the switching stage.

A distributed amplifier includes a first transmission line for input, a second transmission line for output, an input termination resistor connecting a line end of the first transmission line and a power supply voltage, an output termination resistor connecting an input end of the second transmission line and a ground, unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, and a bias tee configured to supply a bias voltage to an input transistor of each of the unit cells. An emitter or source resistor of the input transistor of each of the unit cells is set to a different resistance value from each other in order for a collector or drain current flowing through the input transistor of each of the unit cells to have a uniform value.

A distributed amplifier includes a first transmission line for input, a second transmission line for output, an input termination resistor connecting a line end of the first transmission line and a power supply voltage, an output termination resistor connecting an input end of the second transmission line and a ground, unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, and a bias tee configured to supply a bias voltage to an input transistor of each of the unit cells. An emitter or source resistor of the input transistor of each of the unit cells is set to a different resistance value from each other in order for a collector or drain current flowing through the input transistor of each of the unit cells to have a uniform value.

An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors and intended to receive an adjustable calibration voltage, and the sources of the first transistors are directly connected to a cold power supply point.

A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

An image rejection mixer includes a delay circuit for delaying one of first signals divided by a distribution circuit and a second signal provided to a second mixing circuit by the same delay amount d, or delaying the other one of the first signals divided by the distribution circuit and the second signal provided to a first mixing circuit by the same delay amount d.