A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

A transmitter that reduces 3.sup.rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.

A transmitter that reduces 3.sup.rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.

A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor. The first capacitor includes a first terminal coupled to the first terminal of the capacitor circuit, and a second terminal coupled to the control terminal of the first transistor.

A mixer module includes a mixer, at least one DC offset circuit, a filter and a controller. The mixer mixes an input signal to generate a first signal. The at least one DC offset circuit generates a second signal based on the first signal. The filter filters out an AC portion of the second signal and generates a third signal according to a DC portion of the second signal. The controller controls the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal.

A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor. The first capacitor includes a first terminal coupled to the first terminal of the capacitor circuit, and a second terminal coupled to the control terminal of the first transistor.

A mixer module includes a mixer, at least one DC offset circuit, a filter and a controller. The mixer mixes an input signal to generate a first signal. The at least one DC offset circuit generates a second signal based on the first signal. The filter filters out an AC portion of the second signal and generates a third signal according to a DC portion of the second signal. The controller controls the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal.

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

A direct current (DC) offset calibration device and a method are used to calibrate a DC offset of a unit. The DC offset calibration device includes a signal generation unit, a to-be-calibrated unit, a measurement unit, and a compensation unit. The DC offset calibration method includes: using the to-be-calibrated unit to output a clipped signal resulting from a signal saturation effect; receiving a receiving signal correlated to the clipped signal, the receiving signal including an even harmonic resulting from the clipped signal; measuring a magnitude of the even harmonic to obtain a DC offset adjustment value accordingly; and adjusting the to-be-calibrated unit according to the DC offset adjustment value to calibrate the DC offset.

The present invention relates to a method and an apparatus for direct current offset calibration of a direct conversion receiver, a Direct Current (DC) offset calibration apparatus of a direct conversion receiver includes a plurality of variable gain amplifiers for amplifying an input signal based on a gain control value, a DC offset monitoring unit for monitoring a DC offset for an output signal of the plurality of variable gain amplifiers, a plurality of variable Digital to Analog Converters (DACs) for controlling a current applied to each of the plurality of variable gain amplifiers according to a current control code, and a DC offset cancellation unit for determining a current control code set which minimizes the DC offset value per preset gain control value, and thus the DC offset can be precisely cancelled without being affected by external factors such as a signal modulation method and heat and performance degradation of the receiver can be prevented.