In an example, a system includes an amplifier configured to produce a bandgap voltage reference. The system also includes a current source configured to provide a current to bias the amplifier. The system includes a switching circuit configured to receive a first current replica signal and a second current replica signal, the switching circuit further configured to cause the current source to provide the current to bias the amplifier based on either the first current replica signal or the second current replica signal.

In an example, a system includes an amplifier configured to produce a bandgap voltage reference. The system also includes a current source configured to provide a current to bias the amplifier. The system includes a switching circuit configured to receive a first current replica signal and a second current replica signal, the switching circuit further configured to cause the current source to provide the current to bias the amplifier based on either the first current replica signal or the second current replica signal.

A circuit system for providing thermal stability to a transistor may include: a comparing circuit in electrical communication with the transistor for receiving a present voltage from the transistor and comparing a present voltage to a predetermined bias voltage; a logic gate electronically coupled to an output of the comparing circuit, the logic gate, gate having a high, open position and a low, closed position; and a heating element thermally coupled to the transistor and electrically coupled to the output of the comparing circuit, wherein when the present voltage is lower than the predetermined bias voltage, the gate is in the high, open position providing current to the heating element, and wherein when the present voltage is higher than the predetermine bias voltage the gate is in the low, closed position.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

Power amplifiers having improved gate oxide integrity are disclosed. In particular, a dynamic asymmetric cascode bias circuit is used to provide a bias signal to a cascode power amplifier stage. The bias signal swings in synchronicity with an output signal from the power amplifier stage. By having this dynamic bias signal, the gate-drain stress on the device is reduced, preserving gate oxide integrity. Preserving gate oxide integrity helps preserve the operational profile and extend device life, providing an enhanced user experience.

A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.

This disclosure relates generally to the field of wireless communication infrastructure, and more particularly to a method, apparatus and system for envelope tracking. The system for envelope tracking comprising: a transistor; an RF transistor; a driver; a switcher current source; and a subtracting network; wherein the system is configured such that when an envelope voltage is less than a predetermined voltage value, the RF transistor is configured for decreasing an amount of absorbed biasing current, and when the envelope voltage is greater than a predetermined voltage value, the RF transistor is configured for increasing an amount of absorbed biasing current. The goal of RF transistor sinking is to absorb the redundant biasing current generated by the envelope tracking supply modulator to eliminate distortions.

Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.