An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port V.sub.in and an output port V.sub.out to form a differential input stage and N subsequent gain stages, a capacitive load C.sub.L coupled to the output port V.sub.out, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ω.sub.t of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ω.sub.t.

An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2π.Math.fc.Math.C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.

A power amplifier unit includes a power amplifier circuit that amplifies a radio-frequency input signal, a first impedance matching circuit that performs impedance matching for an output signal of the power amplifier circuit, a second-order harmonic termination circuit on an output side of the first impedance matching circuit and that reflects at least part of even-ordered and odd-ordered harmonics contained in a signal input from the first impedance matching circuit to output the at least part of the harmonics from an input terminal as a radio-frequency signal and outputs a radio-frequency signal containing a fundamental and the remainder of the harmonics from an output terminal, and a filter that is on a subsequent stage of the second-order harmonic termination circuit, that attenuates at least part of the even-ordered and odd-ordered harmonics, and that outputs a radio-frequency signal including the fundamental and the remainder of the even-ordered and odd-ordered harmonics.

A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes a first stage, configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal, and a second stage, configured to convert the single-ended voltage signal provided by the first stage to a differential signal. In such a TIA, the input linear range may be adjusted using a clamp that is programmable with an output offset current to keep the second stage of the TIA from overloading and to maintain a linear transfer function without compression.

According to one embodiment, a semiconductor circuit includes a first transimpedance amplifier and a second transimpedance amplifier. The first transimpedance amplifier is configured to convert an input current to a first output voltage and output the first output voltage from a first output terminal when a reference voltage is supplied to a first input terminal and the input current is supplied to a second input terminal. The second transimpedance amplifier has a circuit configuration similar to a circuit configuration of the first transimpedance amplifier. The second transimpedance amplifier is configured to output a second output voltage from a second output terminal when the reference voltage is supplied to a third input terminal.

A reception circuit includes an input terminal configured to receive an input current; a voltage signal circuit being configured to convert a current signal into a voltage signal; a reference voltage circuit configured to generate a reference voltage in accordance with a first feedback current; a differential amplifier circuit configured to generate a differential signal in accordance with a voltage difference between the voltage signal and the reference voltage; and an offset control circuit configured to generate the first feedback current and a second feedback current, adjust the first feedback current when the voltage signal has an average voltage value greater than the reference voltage, and subtract the second feedback current from the input current such that the offset of the differential signal falls within the tolerance when the voltage signal has an average voltage value smaller than the reference voltage.

It is described a charge preamplifier device (100) integrated in a chip (200) of semiconductive material comprising: an input (IN) for an input signal (i.sub.IN) and an output (OUT) for an output signal (v.sub.OUT); a substrate (202) of semiconductive material doped according to a first type of conductivity; an electrically insulating layer (204) placed on said substrate (202); a feedback capacitor (C.sub.f) integrated in the chip (200) and comprising a first electrode (3) connected to the input (IN) and a second electrode (2) connected to the output (OUT). The second electrode (2) is formed by a doped conductive region (205) having a second type of conductivity, opposite to the first type of conductivity, and integrated in the substrate (202) in order to face the first electrode (3).

An amplifier circuit includes an amplifier and an output transistor. The amplifier is coupled to an output node of the output transistor for providing an output voltage to a load device. The amplifier circuit also includes a slew-rate control circuit coupled to a gate node of the output transistor and configured to control voltage rise of the gate node of the output transistor during power-up to reduce output voltage overshoot.

A high-linearity amplifier including a main operational amplifier, a feedback circuit, and a compensation circuit is shown. The feedback circuit couples an output signal of the main operational amplifier to an input port of the main operational amplifier. The compensation circuit couples a former-stage circuit of the amplifier to the input port of the main operational amplifier to compensate for the non-linearity of the feedback circuit. The compensation circuit and the feedback circuit form an inverse paralleling linearization architecture. In the inverse paralleling linearization architecture, a resistor in the feedback circuit corresponds to a resistor in the compensation circuit which is biased in an inversed way in comparison with the corresponding resistor in the feedback circuit.

An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.