A broadband power amplifier device includes an input matching network including first, second and third inductors, a driver amplifier, and first, second and third frequency modulators. First inductor has one end connected to output of a mixer and the other end connected to one end of the first frequency modulator, with the other end of the first frequency modulator being grounded. The second inductor has one end connected to one end of first inductor and the other end connected to input of driver amplifier, with second frequency modulator being connected across second inductor. Third inductor has one end connected to output of driver amplifier and the other end connected to input of power amplifier, with third frequency modulator being connected across third inductor. Bandwidth of power amplifier device can be extended and area and current consumption thereof can be reduced, while power can be improved without large LO driver.

A broadband power amplifier device includes an input matching network including first, second and third inductors, a driver amplifier, and first, second and third frequency modulators. First inductor has one end connected to output of a mixer and the other end connected to one end of the first frequency modulator, with the other end of the first frequency modulator being grounded. The second inductor has one end connected to one end of first inductor and the other end connected to input of driver amplifier, with second frequency modulator being connected across second inductor. Third inductor has one end connected to output of driver amplifier and the other end connected to input of power amplifier, with third frequency modulator being connected across third inductor. Bandwidth of power amplifier device can be extended and area and current consumption thereof can be reduced, while power can be improved without large LO driver.

Disclosed is an apparatus comprising means for transmitting a first signal via at least a first switch, a first amplifier, a second switch and a power amplifier, wherein an output of the second switch is connected to a power amplifier path comprising at least the power amplifier, while transmitting the first signal. An input of the first switch and the output of the second switch are switched to switch between transmitting and receiving. A second signal is received via at least the first switch, the first amplifier and the second switch, wherein the output of the second switch is disconnected from the power amplifier path while receiving the second signal.

An apparatus measures a speaker impedance. A DAC converts a known digital input signal to an audio frequency first analog voltage signal. Resistors with known resistance attenuate the first analog voltage signal to generate a current. The known resistance effectively determines the current because the known resistance is high relative to the speaker impedance. The current is sourced into the speaker to generate a second analog voltage signal. The known resistance is sufficiently high to cause the second analog voltage signal to be inaudible as transduced by the speaker. An amplifier amplifies the second analog voltage signal with a known gain to generate a third analog voltage signal. An ADC converts the third analog voltage signal to a digital output signal. A processing element calculates the impedance of the speaker proportional to the digital output signal based on the known digital input signal, the known resistance, and the known gain.

Disclosed is a configurable dual vacuum tube triode amplifier. The amplifier comprises two vacuum tube triodes and a user configurable switching component. The user configurable switching component can be positioned into at least a first position and a second position to modify an arrangement of the two vacuum tube triodes to provide varying tonal characteristics of the amplifier. Positioning the user configurable switching component in the first position arranges the two vacuum tube triodes in a cascode configuration to achieve a tonal characteristic of a vacuum tube pentode. Positioning the multi-position user switch in the second position arranges the two vacuum tube triodes in either a single vacuum tube triode configuration to achieve a tonal characteristic of a single vacuum tube triode operating alone or two vacuum tube triodes operating in a parallel configuration to achieve the tonal characteristics of two vacuum tube triodes operating in parallel.

A circuit for predistortion, comprising a digital predistorter configured to generate a modified digital signal by modifying an input baseband signal with a predistortion coefficient; a DAC configured to generate an analog signal by converting the modified digital signal; a PA configured to generate an amplified signal by amplifying the analog signal; an attenuator configured to generate an attenuated signal by attenuating the amplified signal; an ADC configured to generate a attenuated digital signal; a timing synchronizer configured to generate a synchronized amplified signal by synchronizing the attenuated digital signal with the modified digital signal; a statistics generator configured to generate a probability density function of a plurality of samples of the input baseband signal; an orthogonal basis function generator configured to generate a set of normalized orthogonal basis functions; a predistortion coefficient training circuit configured to generate an updated predistortion coefficient.

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.