A compensation circuit, chip, method and device, a storage medium, and an electronic device are disclosed. The compensation circuit may include an analog module (102) including an input node (1022) and an output node (1024), wherein the input node (1022) is configured to receive an input signal and the output node (1024) is configured to output an output signal; and a linearity compensation module (104) including a plurality of transconductance units (1042), where the plurality of transconductance units (1042) are configured to acquire a first configuration signal and configure a combination of the plurality of transconductance units (1042) based on the first configuration signal to provide a compensation signal to the output node (1024), and the first configuration signal is configured to indicate a signal at any position in the analog module (102).

According to at least one example of the disclosure, a power amplifier is provided comprising a first power switch of a first type being configured to receive an input signal and provide an amplified output signal to an output connection configured to be coupled to a load, and a second power switch of a second type different than the first type, the second power switch being configured to improve a linearity of the power amplifier and being coupled to the output connection.

A low noise amplifier topology can achieve very low noise figure by applying multiple magnetic coupling between gate matching inductors and source degeneration inductor of a field effect transistor. The resulting low noise amplifier has smaller inductors, which can have lower thermal noise contribution, and can maintain good gain and linearity performance. For example, a low noise amplifier includes a first inductor to receive an input; a second inductor coupled to the first inductor in series; a first field effect transistor device whose gate receives a signal from the second inductor; and a third inductor coupled to a source of the first field effect transistor device, where the third inductor is magnetically positively coupled to the first inductor and the second inductor.

A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

It is disclosed an amplifier for driving a capacitive load, comprising an input terminal adapted to receive an input voltage signal, an output terminal adapted to drive the capacitive load, a linear amplification stage, switching amplification stage, a capacitor, a first switch and a measurement and control circuit. The measurement and control circuit is configured to: measure the value of the current generated at the output from the linear amplification stage and generate a driving voltage signal of the switching amplification stage; generate the first switching signal to open the first switch and generate an enabling signal to enable the operation of at least part of the switching amplification stage; generate the first switching signal to close the first switch and generate the enabling signal to disable the operation of the switching amplification stage; generate the first switching signal to open the first switch.

Examples of amplifiers and n.sup.th-order loop filters thereof are configured to enable fast and robust recovery from saturation, while limiting signal distortion at or near full power delivery across multiple process and temperature corners. An example n.sup.th-order loop filter comprises n series-coupled resistor-capacitor (RC) integrators. In an example, each of the second RC integrator to the (n−1).sup.th RC integrator has a reset mechanism responsive to a reset signal output from a reset controller when an input signal overload condition is detected at the input. Upon detecting the overload condition, each of the third RC integrator to the (n−1).sup.th RC integrator is hard reset, the n.sup.th RC integrator is not reset, and a controlled reset is performed on the second RC integrator to recover from saturation caused by the signal overload condition, while maintaining the output signal below the 1% total harmonic distortion (THD) level at or near full power delivery.

Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such front end system includes a low noise amplifier in a receive path and a multi-mode power amplifier circuit in a transmit path. An overload protection circuit can adjust an impedance of a switch coupled to the low noise amplifier based on a signal level of the low noise amplifier. The multi-mode power amplifier circuit includes a stacked output stage including a transistor stack of two or more transistors. The multi-mode power amplifier circuit also includes a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.

An RF amplifier utilizes first and second main amplifiers in a balanced amplifier configuration with first and second auxiliary amplifiers connected in parallel across the first and second main amplifiers, respectively. The main and the auxiliary amplifiers are biased such that the third-order nonlinearity components in the combined output current are reduced. A common or independent bias control circuit(s) control(s) the DC operating bias of the auxiliary amplifiers and establishes DC operating points on curves representing third-order nonlinear components within the drain current having a positive slope (opposite to the corresponding slope of the main amplifiers). This results in reduction of overall third-order nonlinear components in combined currents at the output. In another embodiment, a phase shift of an input to one auxiliary amplifier is used to provide a peak in minimization at a frequency associated with the phase shift.

An amplifier circuit having an adjustable gain is provided. The amplifier circuit includes an input terminal, an output terminal, an amplifier, and an attenuation circuit. The input terminal receives an input signal, which is in turn received by an input terminal of the amplifier. An output terminal of the amplifier outputs the input signal that is amplified. The attenuation circuit is coupled between the output terminal of the amplifier and the output terminal to provide a plurality of attenuation to the input signal that is amplified and generate a first attenuation signal, or between the input terminal and the output terminal to provide the plurality of attenuations to the input signal and generate a second attenuation signal. A difference between an impedance value of the input terminal of the attenuation circuit and an impedance value of the output terminal of the attenuation circuit is within a predetermined range.

A bias circuit includes first to fourth transistors and a phase compensation circuit. In the first transistor, a reference current or voltage is supplied to a first terminal, and the first terminal and a second terminal are connected. In the second transistor, a first terminal is connected to the first transistor, and a third terminal is grounded. In the third transistor, a power supply voltage is supplied to a first terminal, a second terminal is connected to the first transistor, and a bias current or voltage is supplied from a third terminal to an amplifier transistor. In the fourth transistor, a first terminal is connected to the third transistor, a second terminal is connected to the second transistor, and a third terminal is grounded. The phase compensation circuit is provided in a path extending from the fourth transistor to the third transistor through the second and first transistors.