Transconductor circuits with programmable tradeoff between bandwidth and flicker noise are disclosed. An example circuit includes an input port, an output port, a plurality of transistors, and a switch arrangement that includes a plurality of switches, configured to change coupling between the input port, the output port, and the transistors to place the transconductor circuit in a first or a second mode of operation. An input capacitance of the transconductor circuit operating in the first mode is larger than when the transconductor circuit is operating in the second mode. In the first mode, having a larger input capacitance results in a decreased flicker noise because the amount of flicker noise is inversely proportional to the input capacitance. In the second mode, having a smaller input capacitance leads to an increased flicker noise but that is acceptable for wide-bandwidth applications because wide-bandwidth signals may be less sensitive to flicker noise.

Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.

Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.

A continuous time linear equalizer (CTLE) includes a first circuit path having a step response that increases from an first initial value to a steady state value higher than the first initial value. The CTLE also includes a second circuit path in parallel with the first circuit path, the second circuit path having a step response that increases from a second initial value to a peak and subsequently falls to second steady state value that is approximately equal to the second initial value. The CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.

Apparatus and methods for a low-load-modulation power amplifier are described. Low-load-modulation power amplifiers can include multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see low modulation of its load between the power amplifier's fully-on and fully backed-off states. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained.

Aspects of the subject disclosure may include a power splitter. The power splitter can include a first splitter branch having a first amplifier with passive components, a second splitter branch having a second amplifier with passive components. The first splitter branch is substantially electrically isolated from the second splitter branch by configuring the first and second splitter branches to have similar phase delays. Outputs of the power splitter can be electrically coupled to the multi-stage amplifier. The power splitter can be manufactured on a single semiconductor die or integrally formed on the same semiconductor die with other circuits such as the multi-stage amplifier. Other embodiments are disclosed.

Aspects of the subject disclosure may include a power splitter. The power splitter can include a first splitter branch having a first amplifier with passive components, a second splitter branch having a second amplifier with passive components. The first splitter branch is substantially electrically isolated from the second splitter branch by configuring the first and second splitter branches to have similar phase delays. Outputs of the power splitter can be electrically coupled to the multi-stage amplifier. The power splitter can be manufactured on a single semiconductor die or integrally formed on the same semiconductor die with other circuits such as the multi-stage amplifier. Other embodiments are disclosed.

Embodiments of the present disclosure include a harmonic power amplifying circuit with high efficiency and high bandwidth and a radio-frequency power amplifier. The circuit comprises an input matching network (11), a transistor (M), and an output matching network (12); a gate of the transistor (M) connected to an output end of the input matching network (11), a drain thereof connected to an input end of the output matching network (12), and a source thereof being grounded; wherein the output matching network (12) enables a lower sideband of the harmonic power amplifying circuit to work in a continuous inverse F amplification mode and an upper sideband of the harmonic power amplifying circuit to work in a continuous F amplification mode; wherein the output matching network (12) and a parasitic network of the transistor (M) form a low pass filter. By transitioning from the continuous inverse F power amplifier working mode to the continuous F power amplifier working mode, the efficiency of a continuous harmonic control power amplifier is effectively improved to be higher than 60%, a relative bandwidth is improved to be higher than 80%, and the harmonic impedance is simple to match and easy to realize.

A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a differential PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.

A differential amplifier is provided. The differential amplifier includes a first single-ended amplifying means including at least a first terminal and a second terminal, a second single-ended amplifying means including at least a first terminal and a second terminal, a first transmission line, and a second transmission line. In this context, the first terminal of the first single-ended amplifying means is connected to the second terminal of the second single-ended amplifying means via the first transmission line. In addition to this, the first terminal of the second single-ended amplifying means is connected to the second terminal of the first single-ended amplifying means via the second transmission line.