A semiconductor device is provided with one or more gate fingers (20) that are provided in an active region on a semiconductor substrate (1), and a source finger (30) and a drain finger (40) that are provided in the active region and arranged alternately to allow each gate finger to be sandwiched between the source and drain fingers. The semiconductor device includes terminal circuit (60) that has inductive impedance at the frequency of a signal input to an input terminal of the one or more gate fingers, and is directly or indirectly connected to the one or more gate fingers at an area being spaced away from a connecting position of the input terminal (21a) of the one or more gate fingers (20).

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

An audio reproduction apparatus is shown and includes an amplifier with a power amplification stage having transistors in a push-pull arrangement. A bias generator biases the transistors with a standing current. A processor receives a data stream comprising digital samples of an analog audio signal and analyzes the peak level of each group. It then determines the appropriate standing currents to maintain Class A operation of the power amplification stage given the peak levels of each of the groups. A digital to analog converter produces an analog input signal for the input stage of the amplifier from the data stream. A feedforward path between the processor and the bias generator allows the standing current to be adjusted prior to the arrival of the analog input signal in the power amplification stage.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A bias circuit for a Doherty amplifier, characterized by comprising: an input port with an input impedance, wherein the input port is configured to receive a bias signal from a power supply; a first output port configured to provide a bias signal to an amplifier; a second output port configured to provide a bias signal to an amplifier; a two port impedance transformer with an input connected to the first input port, and an output of the two port impedance transformer having an intermediate impedance; an in-phase N-port dividing impedance transformer with an input connected to the output of the two port impedance transformer, wherein the in-phase N-port dividing impedance transformer comprises: a first output connected to the first output port having a first output impedance; and a second output connected to the second output port having a second output impedance.

A bias circuit for a Doherty amplifier, characterized by comprising: an input port with an input impedance, wherein the input port is configured to receive a bias signal from a power supply; a first output port configured to provide a bias signal to an amplifier; a second output port configured to provide a bias signal to an amplifier; a two port impedance transformer with an input connected to the first input port, and an output of the two port impedance transformer having an intermediate impedance; an in-phase N-port dividing impedance transformer with an input connected to the output of the two port impedance transformer, wherein the in-phase N-port dividing impedance transformer comprises: a first output connected to the first output port having a first output impedance; and a second output connected to the second output port having a second output impedance.

A radio frequency circuit has an amplifier that amplifies an input radio frequency signal, a power supply path that is disposed between an output node of the amplifier and a power supply node to which a DC bias voltage is supplied, and includes a first inductor and a second inductor connected in series, a first resonator that comprises a third inductor and a first capacitor connected in series to the third inductor, and resonates at a series resonance frequency, a second resonator that resonates at a series resonance frequency corresponding to an inductance of the first inductor, a capacitance of the second capacitor, and a resistance value of the first resistor, and a third resonator that comprises a third capacitor connected in parallel with the second inductor, and resonates at a parallel resonance frequency corresponding to a capacitance of the third capacitor and an inductance of the second inductor.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

The present disclosure relates to an envelope tracking (ET) amplification architecture, which includes a power amplifier (PA) block configured to amplify a radio frequency (RF) input signal and provide an RF output signal, and an ET voltage block configured to provide modulated voltages to the PA block as power supplies. Herein, the modulated voltages are provided based on a configuration of the PA block and from one pulsed ramp signal, which contains envelope information of the RF input signal. The modulated voltages are eligible to have at least one of a time delay difference, an amplitude difference, and a phase difference.