Aspects of the disclosure relate to a local oscillator frequency divider for a receiver or transmitter. In this regard a frequency divider has a first frequency input coupled to a first oscillator frequency output, a second frequency input coupled to a complementary second oscillator frequency output, a first in-phase/quadrature (I/Q) divided frequency output, and a complementary second I/Q divided frequency output. The frequency divider further has a first alternating current (AC) coupling capacitor between the first frequency input and the first oscillator frequency output and a second AC coupling capacitor between the second frequency input and the second oscillator frequency output.

A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.

Circuits and operating methods thereof for correcting phase errors introduced by amplifiers employing gallium nitride (GaN) transistors are described. The phase errors are caused by trapping effects exhibited by the GaN transistors. The circuits described herein pre-distort the phase of the input signal to compensate for the phase error introduced by the amplifier. Thereby, the phase of the output signal of the amplifier has a reduced phase error. For example, the output signal may have a near zero (or zero) phase error.

Thermal temperature sensors for power amplifiers are provided herein. In certain implementations, a semiconductor die includes a compound semiconductor substrate, and a power amplifier including a plurality of field-effect transistors (FETs) configured to amplify a radio frequency (RF) signal. The plurality of FETs are arranged on the compound semiconductor substrate as a transistor array. The semiconductor die further includes a semiconductor resistor configured to generate a signal indicative of a temperature of the transistor array. The semiconductor resistor is located adjacent to one end of the transistor array.

Loss in a low-pass filter is reduced. A radio-frequency module includes an antenna terminal, a power amplifier, a low-noise amplifier, and a low-pass filter. The low-pass filter is disposed on a transmit path between the antenna terminal and the power amplifier and on a receive path between the antenna terminal and the low-noise amplifier. The low-pass filter has multiple paths. Each of the paths forms a part of either one or both of the transmit path and the receive path. The paths include a first path and a second path. The second path has a smaller reactance than the first path.

Embodiments of the present disclosure include a harmonic power amplifying circuit with high efficiency and high bandwidth and a radio-frequency power amplifier. The circuit comprises an input matching network (11), a transistor (M), and an output matching network (12); a gate of the transistor (M) connected to an output end of the input matching network (11), a drain thereof connected to an input end of the output matching network (12), and a source thereof being grounded; wherein the output matching network (12) enables a lower sideband of the harmonic power amplifying circuit to work in a continuous inverse F amplification mode and an upper sideband of the harmonic power amplifying circuit to work in a continuous F amplification mode; wherein the output matching network (12) and a parasitic network of the transistor (M) form a low pass filter. By transitioning from the continuous inverse F power amplifier working mode to the continuous F power amplifier working mode, the efficiency of a continuous harmonic control power amplifier is effectively improved to be higher than 60%, a relative bandwidth is improved to be higher than 80%, and the harmonic impedance is simple to match and easy to realize.

A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.

One example includes a differential amplifier, a voltage weighting element, coupled to a voltage source which provides an input voltage, to provide a reference voltage with a constant power limit when the input voltage varies, an error amplifier configured to receive and compare the reference voltage provided from the voltage weighting element and a feedback sensed voltage provided from the differential amplifier to identify whether the sensed voltage exceeds the reference voltage, and a pulse width modulation (PWM) controller, coupled to a power transformer and the error amplifier, that reduces a transformer input current provided to the power transformer based on the comparison of the reference voltage from the voltage weighting element and the feedback sensed voltage from the differential amplifier.

A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.

An ECG signal acquisition system includes a first amplifier which has a non-inverting input adapted to be coupled to a first differential input, an inverting input adapted to be coupled to a second differential input, and an output. The system includes first and second biasing resistors coupled between the non-inverting and inverting inputs of the first amplifier. The system includes an average estimation circuit which has a first input coupled to the non-inverting input of the first amplifier and a second input coupled to the inverting input of the first amplifier. The system includes a driver amplifier which has an inverting input coupled to the output of the average estimation circuit, a non-inverting input coupled to receive a reference common-mode voltage, and an output. The system includes a low-pass filter coupled between the output of the driver amplifier and the biasing resistors.