An RF amplifier includes an amplifier input, a transistor die with a transistor and a transistor input terminal, a fundamental frequency impedance matching circuit coupled between the amplifier input and the transistor input terminal, and a harmonic frequency termination circuit coupled between the transistor input terminal and a ground reference node. The harmonic frequency termination circuit includes a first inductance coupled between the transistor input terminal and a first node, and a tank circuit coupled between the first node and the ground reference node. The tank circuit includes a first capacitance coupled between the first node and the ground reference node, and a second inductance coupled between the first node and the ground reference node. The tank circuit is configured to shunt signal energy at or near a second harmonic frequency, while appearing as an open circuit to signal energy at a fundamental frequency of operation of the RF amplifier.

Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.

A radio frequency (RF) amplifier and a bias circuit are provided. The RF amplifier includes an amplifier, a first inductive-capacitive resonance circuit, and a first bias circuit. The amplifier includes an input terminal configured to receive an incoming RF signal through a first RF path. The first inductive-capacitive resonance circuit includes a first terminal coupled to a first reference voltage. A second terminal of the first inductive-capacitive resonance circuit is coupled to the first RF path. In response to the first reference voltage being at a first reference level, the RF amplifier is enabled; in response to the first reference voltage being at a second reference level, the RF amplifier is disabled. The first bias circuit includes a first terminal configured to be coupled to the first reference voltage and a second terminal coupled to the input terminal of the amplifier to provide a first direct current (DC) component.

CRLH lines including left-handed shunt inductors and left-handed series capacitors are provided on gate side transmission lines of a plurality of FETs.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.

A power amplifier includes an outphasing amplifier. The outphasing amplifier includes a first amplifier and a second amplifier, and is configured to provide a first amplified RF signal and a second amplified RF signal that is phase shifted from the first amplified RF signal. The power amplifier further includes an output circuit that is configured to combine RF power of the first and second amplified RF signals at a summing node. The output circuit includes a first branch connected between the first amplifier and a summing node and a second branch connected between the second amplifier and the summing node. The first and second branches are each configured to match an output impedance of the first and second amplifiers and to phase shift the first and second amplified RF signals for an outphasing operation using common reactive components for the match of the output impedance and the outphasing operation.

The present disclosure includes dynamic power divider circuits and methods. In one embodiment, a dynamic power divider includes first and second quarter wave lines that receive an input signal and produce first and second signal on second terminals of the lines. Dynamic power division of the input signal uses a variable impedance circuit between the second terminal of the first quarter wave line and the second terminal of the second quarter wave line. The variable impedance may reduce impedance between two output paths as the input signal power increases or increase impedance between the output paths as the input signal power decreases.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A low-noise amplifier is provided. The low-noise amplifier includes a first transistor configured to amplify an input signal; a second transistor which forms a cascade structure with the first transistor and configured to amplify an output signal of the first transistor; and a third transistor which forms a cascode structure together with the first transistor and configured to amplify the output signal of the first transistor, wherein a first signal including a sum of the output signal of the second transistor and the output signal of the third transistor is output to an output terminal.