Distributed amplifier systems and methods are disclosed. An example distributed amplifier system includes first stage traveling wave amplifier (TWA) circuitry that is controllable to provide one of a first set of discrete gain settings. The first stage TWA circuitry includes a first input transmission line, a first output transmission line, and a first plurality of amplifiers coupled antiparallel between the first input transmission line and the first output transmission line. The first set of discrete gain settings has approximately constant logarithmic spacing.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a tunable radio frequency (RF) low noise amplifier (LNA) circuit including an amplifier circuit, where the amplifier circuit is configured to receive an input RF signal from an RF input source and provide an amplified output RF signal, a bias resistor, where a first end of the bias resistor is operatively coupled to an input of the amplifier circuit, a digitally programmable bias circuit operatively coupled to a second end of the bias resistor, where the bias circuit outputs a reference voltage, and a programmable input impedance circuit operatively coupled between the first end of the bias resistor and a ground. The programmable input impedance circuit includes an input transconductor transistor and a programmable inductance network.

An exemplary embodiment of a low noise amplifier has integral noise cancellation to provide a low noise figure and operation over a frequency range of 40 GHz-60 GHz. An amplifier amplifies an input signal as well as noise present with the amplified signal and amplified noise being out of phase and in phase, respectively, with the corresponding inputs. An auxiliary amplifier amplifies the same inputs and generates an amplified signal and amplified noise both being out of phase relative to the inputs. A summation circuit combines all of these amplified signals with the noise being cancelled since the auxiliary amplifier provides the same amount of amplification as the amplifier and the amplified noise signals being summed are 180 degrees out of phase to each other. Preferably, the amplifier, auxiliary amplifier and the summation device utilize CMOS transistors disposed on an SOI substrate with impedance stabilization over the frequency range.

An exemplary embodiment of a low noise amplifier has integral noise cancellation to provide a low noise figure and operation over a frequency range of 40 GHz-60 GHz. An amplifier amplifies an input signal as well as noise present with the amplified signal and amplified noise being out of phase and in phase, respectively, with the corresponding inputs. An auxiliary amplifier amplifies the same inputs and generates an amplified signal and amplified noise both being out of phase relative to the inputs. A summation circuit combines all of these amplified signals with the noise being cancelled since the auxiliary amplifier provides the same amount of amplification as the amplifier and the amplified noise signals being summed are 180 degrees out of phase to each other. Preferably, the amplifier, auxiliary amplifier and the summation device utilize CMOS transistors disposed on an SOI substrate with impedance stabilization over the frequency range.

A low noise amplifier has integral noise cancellation to provide a low noise figure and operation over a frequency range of 0.5 GHz-50 GHz. An amplifier amplifies an input signal as well as noise present with the amplified signal and amplified noise being out of phase and in phase, respectively, with the corresponding inputs. A feedback circuit that is non-linear with frequency enables a constant amplification. A summation circuit combines amplified signals with the noise being cancelled since two combined noise signals being summed are 180 degrees out of phase to each other. An optional secondary amplification stage provides additional amplification. Preferably, the amplifier, auxiliary amplifier and the summation device utilize CMOS transistors disposed on an SOI substrate with impedance stabilization over the frequency range.

Distributed amplifier systems and methods are disclosed. An example distributed amplifier system includes first stage traveling wave amplifier (TWA) circuitry that is controllable to provide one of a first set of discrete gain settings. The first stage TWA circuitry includes a first input transmission line, a first output transmission line, and a first plurality of amplifiers coupled antiparallel between the first input transmission line and the first output transmission line. The first set of discrete gain settings has approximately constant logarithmic spacing.

A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.

Examples of input stages of circuits are configured to reduce both negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) in PMOS transistors therein. Current-switched PMOS source follower transistors and a low-side NMOS differential pair is used to process a lower range of a rail-to-rail input signal range of a circuit. A PMOS source follower is disposed between the positive input of the circuit and the positive input of the low-side NMOS differential pair. Another PMOS source follower is disposed between the negative input of the circuit and the negative input of the low-side NMOS differential pair. Various arrangements are provided for generating and maintaining the bias currents of the two PMOS source followers to be approximately the same through the entire lower input signal range.