A Doherty amplifier is configured in such a way that a phase adjustment circuit adjusts either the phase of a return signal going to a first auxiliary amplification element as a result of passage of a first signal amplified by a second main amplification element through a second auxiliary amplification element as the return signal, or the phase of the return signal going to the second auxiliary amplification element as a result of reflection of the return signal by the first auxiliary amplification element, at a time of a backoff operation of the second auxiliary amplification element, in such a way that the sum of the phase of the return signal going to the first auxiliary amplification element and the phase of the return signal going to the second auxiliary amplification element is not equal to 0 degrees in the operating frequency band of the first signal.

Disclosed is power amplifier circuitry having a bipolar junction power transistor with a base, a collector, and an emitter. The power amplifier circuitry includes bias correction sub-circuitry configured to generate a compensation current substantially opposite in phase and substantially equal in magnitude to an error current passed by a parasitic base-collector capacitance inherently coupled between the base and collector, wherein the bias correction sub-circuitry has a compensation output coupled to the base and through which the compensation current flows to substantially cancel the error current.

A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.

Provided is a bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal. The bias circuit includes: an FET that has a power supply voltage supplied to a drain thereof and that outputs the first bias current or voltage from a source thereof; a first bipolar transistor that has a collector thereof connected to a gate of the FET, that has a base thereof connected to the source of the FET, that has a common emitter and that has a constant current supplied to the collector thereof; and a first capacitor that has one end thereof connected to the collector of the first bipolar transistor and that suppresses variations in a collector voltage of the first bipolar transistor.

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

An amplifier circuit is configured in such a way that the amplifier circuit includes: a first amplifier to amplify a signal to be amplified; an output matching circuit through which the signal amplified by the first amplifier propagates; and a second amplifier to amplify the signal which has propagated through the output matching circuit, and the output matching circuit is a lumped constant circuit including multiple lumped constant elements, and, by using the multiple lumped constant elements, transforms the impedance seen on the second amplifier side from the first amplifier when the output power of the second amplifier is lower than saturation electric power, to impedance higher than impedance seen on the second amplifier side from the first amplifier when the output power of the second amplifier is equal to the saturation electric power.

Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.

A power amplifier circuit includes an input-stage power amplifier configured to receive a radio-frequency input signal, an output-stage power amplifier configured to output an amplified radio-frequency output signal, and an intermediate-stage power amplifier disposed between the input-stage power amplifier and the output-stage power amplifier. The intermediate-stage power amplifier includes a first transistor, a second transistor, and a capacitor having a first end connected to an emitter of the first transistor and a second end connected to a collector of the second transistor. The intermediate-stage power amplifier receives a signal at a base of the second transistor thereof and outputs an amplified signal from a collector of the first transistor thereof.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

An amplifier circuit includes a first amplifier that amplifies a high frequency signal, and a load circuit that changes a load impedance of the first amplifier without being controlled by an external circuit so that a saturation power at a first temperature is higher than a saturation power at a second temperature lower than the first temperature, and an efficiency at the first temperature is lower than an efficiency at the second temperature.