Example multi-band phased array are described. One example multi-band phased array includes a plurality of branches coupled to a plurality of multi-band antennas. Each of the plurality of branches includes a low noise amplifier and a power amplifier. The power amplifier and the low noise amplifier are configured to transmit and receive, in a time-sharing manner, a signal of a first frequency band and a signal of a second frequency band that are received by the multi-band phased array, and the first frequency band and the second frequency band are different and do not overlap. Each of the plurality of branches further includes a phase shifter, where the phase shifter is configured to perform phase shifting on the signal of the first frequency band, and the phase shifter is further configured to perform phase shifting on the signal of the second frequency band.

A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.

Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

A device for amplification of an input signal, the device comprising: amplification circuitry comprising a plurality of switchable transistors; a variable voltage input connected to the amplification circuitry; and controller circuitry; wherein the controller circuitry is configured to: set a target output power level of the device; and control at least one of: a state of connection between the plurality of switchable transistors to change an effective physical dimension of the amplification circuitry; or a level of the variable voltage input; in accordance with a load impedance of an output of the amplification circuitry, to amplify the input signal to the target output power level for that load impedance.

A power amplifier including a first transistor for amplifying and outputting a radio frequency signal, a second transistor, a third transistor for supplying a bias current, a first voltage supply circuit for supplying a lower voltage to a base of the third transistor as a temperature of a first diode is higher. The third transistor and the first transistor, or the third transistor and the second transistor, are disposed without another electronic element interposed therebetween. The third transistor is disposed such that a distance between the third transistor and the first transistor is smaller than a distance between the first voltage supply circuit and the first transistor, or a distance between the third transistor and the second transistor is smaller than a distance between the first voltage supply circuit and the second transistor.

Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

In certain aspects, a power amplification device, a power amplification system, and an operation method thereof are disclosed. The power amplification system includes a power amplification device and a control unit. The power amplification device includes a plurality of power amplification circuits, a power supply network configured to supply a power source from a plurality of power sources to the plurality of power amplification circuits, and a transformer network configured to provide an output power that matches a transmit power level. The control unit includes a memory storing code and a processor coupled to the memory. When the code is executed, the processor is configured to determine a plurality of circuit configurations for the plurality of power amplification circuits based on the transmit power level, and configure the plurality of power amplification circuits using the plurality of circuit configurations, respectively, so that the output power matches the transmit power level.

According to one embodiment, a high frequency amplifier circuit includes a first transistor including a gate to which an input signal is input; a second transistor including a gate grounded, and a source coupled to a drain of the first transistor; a first switch coupled between a first output terminal and a first node located between the drain of the second transistor and an inductor; a third transistor including a gate to which the input signal is input; a fourth transistor including a gate that is grounded, and a source coupled to a drain of the third transistor; a second switch coupled between a second output terminal and a second node located between the drain of the fourth transistor and an inductor; and a third switch coupled between the first node and the second node.

A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.