A Doherty amplifier is configured in such a way that a phase adjustment circuit adjusts either the phase of a return signal going to a first auxiliary amplification element as a result of passage of a first signal amplified by a second main amplification element through a second auxiliary amplification element as the return signal, or the phase of the return signal going to the second auxiliary amplification element as a result of reflection of the return signal by the first auxiliary amplification element, at a time of a backoff operation of the second auxiliary amplification element, in such a way that the sum of the phase of the return signal going to the first auxiliary amplification element and the phase of the return signal going to the second auxiliary amplification element is not equal to 0 degrees in the operating frequency band of the first signal.

Amplifier devices includes a first amplifier connected to receive an input voltage. The first amplifier outputs an internal voltage. These structures also include a second amplifier having an input node connected to receive the internal voltage and an output node outputting an output voltage. A resistive feedback loop is connected to the input node and the output node of the second amplifier. A first cross-coupled bandwidth boosting stage is connected to the input node of the second amplifier and a second cross-coupled bandwidth boosting stage connected to the output node of the second amplifier. The cross-coupled bandwidth boosting stages form a distributed differential positive feedback structure.

The present invention is gallium nitride based operational amplifier because reliability and performance of the gallium nitride is better than the silicon counterpart in radiation environment. The operational amplifier includes four stages, first stage is dual input balanced output differential amplifier, second stage is dual input unbalanced differential amplifier, third stage is buffer stage to couple second and fourth stage, and fourth stage is cascaded common source amplifier with degeneration. A capacitor coupled between second and third stage is to enhance the stability of operational amplifier.

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.

A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.

A transceiver is configured for a calibration mode of operation in which an impedance of a transmit chain is tuned responsive to a power measurement of a mixed RF calibration signal to form a tuned transmit chain. A direct conversion mixes an RF calibration signal with a DC offset signal to form the mixed calibration signal. During a normal mode of operation, a heterodyne mixer mixes an LO signal with an IF signal to produce an RF signal that is amplified through the tuned transmit chain.

Apparatus and methods for a low-load-modulation power amplifier are described. Low-load-modulation power amplifiers can include multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see low modulation of its load between the power amplifier's fully-on and fully backed-off states. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained.

The present disclosure relates an interface unit having an input for receiving an input voltage from an electrochemical measuring probe; a first transistor; a first operational amplifier; a second transistor; and a second operational amplifier. The first operational amplifier is arranged to provide a variable tension to a first source terminal of the first transistor, in accordance with a comparison between a reference voltage and a second resistor voltage, in order to control an operating point of the first transistor.

An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.