A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Programmable clamping methods and devices providing adjustable clamping powers to accommodate different applications and requirements are disclosed. The described devices can use switchable clamping circuits having different structures, body-controlled clamping circuits, or clamping circuits adjusting their input power levels using programmable resistive ladders. Examples of how the disclosed devices can be combined to improve design flexibility are also provided.

According to at least one example of the disclosure, a power amplifier system is provided comprising an amplifying transistor configured to amplify a radio frequency signal, a bias circuit configured to provide a bias voltage to the amplifying transistor, and a clamp circuit for protecting the power amplifier system by absorbing a current flowing through the amplifying transistor when the clamp circuit is switched on. The clamp circuit is connected at a bias node between the bias circuit and the amplifying transistor and includes a clamp transistor and a clamp diode, the clamp diode having one end connected to a collector of the clamp transistor at the bias node and another end connected to a base of the clamp transistor.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

Preventing RF signal distortion and signal error producing memory events in a Radio Frequency (RF) power amplifier (RFPA). An element, disposed prior to the Radio Frequency (RF) power amplifier (RFPA) in a signal path of a RF signal input to the RFPA, may enforce a maximum allowable amplitude in a high PAPR instantaneous high peak of the RF signal. An element may also increase or supplement a bias of the Radio Frequency (RF) power amplifier (RFPA) when a high PAPR instantaneous high peak is detected in the RF signal prior to receipt by the RFPA. Additionally, a first element operable detects when an instantaneous output voltage of the Radio Frequency (RF) power amplifier (RFPA) is below a predetermined voltage, and in response, a second element supplies additional current to prevent the output voltage of the RFPA from falling below a predetermined threshold voltage.

Methods and apparatus for limiting the input voltage (swing) of a power amplifier, such as a power amplifier in a radio frequency (RF) front-end of a wireless device. One example radio frequency front-end circuit generally includes a power amplifier, a matching circuit having an output coupled to an input of the power amplifier, and an overvoltage protection circuit coupled to the matching circuit. With an overvoltage protection circuit coupled to the matching circuit in this manner, the power amplifier may have enhanced ruggedness performance.

In described examples, a circuit includes a reference voltage, a driving circuit with a driving input and a driving output, an output transistor, and a clamp circuit with a clamp input and a clamp output. The output transistor includes a source, a drain, and a gate; the source is coupled to receive the reference voltage. The clamp input is coupled to the driving output and to the gate. The clamp output is coupled to either the driving input or to the driving output, the gate, and the clamp input. The clamp circuit is configured to detect an operating region of the output transistor and to generate a clamping current after the output transistor enters a triode region. The clamping current is selected to prevent an absolute value of a source-gate voltage of the output transistor from equaling or exceeding a gate oxide tunneling voltage of the output transistor.

Apparatus and method for detecting and clamping power of a power amplifier are disclosed. In certain embodiments, a power amplifier system includes a power amplifier that amplifies a radio frequency input signal to generate a radio frequency output signal, a bias circuit that controls a bias of the power amplifier, a radio frequency coupler that generates a radio frequency coupled signal based on the radio frequency output signal, a clamp that selectively clamps the bias of the power amplifier, and a power detector that controls the clamp based on the radio frequency coupled signal.

There is provided a to-be-protection circuit that is high in operation accuracy and that prevents overvoltage on a protected circuit. A protection circuit is configured to protect a to-be-protected circuit from overvoltage. The to-be-protected circuit is connected to an external output terminal. The protection circuit includes: a current path unit connected to the external output terminal and including at least one first element; a reference voltage generation unit which generates and outputs a reference voltage; and an amplifier circuit outputs a target voltage based on a difference between a first input voltage and a second input voltage. The amplifier circuit operates using the reference voltage as the first input voltage and using a feedback voltage based on the target voltage as the second input voltage, and outputs the target voltage to the current path unit. The reference voltage generation unit includes at least one second element having an operating characteristic corresponding to an operating characteristic of the at least one first element of the current path unit, and generates the reference voltage based on a voltage drop caused by the at least one second element.

An automated testing system comprises a high side switch circuit coupled to an input/output (I/O) connection, a low side switch circuit coupled to the I/O connection, a high side force amplifier (HFA) coupled to the high side switch, a low side force amplifier (LFA) coupled to the low side switch, an adjusting circuit coupled to the HFA and the LFA, and a control circuit configured to change the adjusting circuit to change control of current at the I/O connection from one of the HFA or LFA to the other of the HFA or LFA.