The disclosure presents a method and an amplifier system for minimizing variation in an acoustical signal caused by variation in gain of an amplifier, comprising a battery for providing a supply voltage to the amplifier, a digital signal processor for providing the acoustical signal to the amplifier, a controller unit receiving an enablement signal when the supply voltage is in an offset mode, and based on the enablement signal requesting a measured voltage during a time period, and a first analog-to-digital converter configured for measuring the supply voltage to the amplifier when receiving the request from the controller unit or the first analog-to-digital converter is configured for measuring the supply voltage to the amplifier continuously, and where variations in the measured voltage relates to variations in the supply voltage during the time period. Furthermore, the controller unit is configured to predict offset modes (i.e. changes) in the supply voltage based on the enablement signals and a fitting of the measured voltages, and wherein the controller unit is configured to generate a compensating signal based on the fitting and transmit the compensating signal to the digital signal processor, the digital signal processor is then configured to minimize variation in the acoustical signal at the output of the amplifier by compensating the variation in gain of the amplifier based on the compensating signal.

An amplifier (300) comprising: a first signal path comprising first amplifier circuitry (105A) configured to receive a first signal (RF1) with a frequency and a variable phase and amplitude at the frequency; a second signal path comprising second amplifier circuitry (105B) configured to receive a second signal (RF2) with the frequency, wherein at least one of the relative phase and amplitude of the second signal is fixed at the frequency; combiner circuitry (106) configured to combine an output of the first amplifier circuitry and the second amplifier circuitry.

A power management circuit supporting phase correction in an analog signal with reduced physical pins is disclosed. The power management circuit includes a power amplifier circuit configured to amplify an analog signal having a time-variant power envelope based on a modulated voltage. The power management circuit also includes an envelope tracking integrated circuit (ETIC) configured to generate the modulated voltage and a modulated phase correction voltage to thereby cause a phase change in the analog signal. The ETIC receives a modulated differential signal that includes a common signal and a differential signal and generates the modulated phase correction voltage and the modulated voltage based on the common signal and the differential signal, respectively. By modulating the common signal and the differential signal into the modulated differential signal, it is possible to reduce physical pins in the ETIC to thereby reduce cost and footprint of the power management circuit.

Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p.sub.1, p.sub.2, . . . , p.sub.k} and a second set of values {s.sub.1, s.sub.2, . . . , s.sub.k} that represent a LUT value of s.sub.1.Math.2.sup.p.sup.1+s.sub.2.Math.2.sup.p.sup.2+ . . . +s.sub.k.Math.2.sup.p.sup.k where each value s.sub.iϵ{+1,−1} where k≥2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p.sub.1, p.sub.2, . . . , p.sub.k} and {s.sub.1, s.sub.2, . . . , s.sub.k} to provide an output sample.

System-on-chip (SOC) products using high frequency, wideband, highly linear, CMOS and BiCMOS processes will be the next evolution of wireless and wireline communications integrated circuits. Aspects described herein can provide enhanced overall performance over existing prior art single-ended, wideband RF amplifier topologies. A single-ended third order intermodulation distortion nulling circuit can extend the dynamic range for wideband amplifiers up to an order-of-magnitude, without a DC power or noise figure (NF) penalty. The application of distortion nulling can be extended to all the building blocks used in CMOS/BiCMOS RF transceivers to improve performance. The application of this concept to all of the building blocks in an RF transceiver will allow the dynamic range of the transceiver to be increased without suffering a DC power dissipation increase or a significant noise increase.

A multichannel transmission system which includes a calibration functionality that allows precise calibration of the frequency conversion chains and of the multiport amplifier of the system to be performed without interruption of service. The proposed calibration makes it possible to correct the defects over the entire frequency band of the system.

Systems and methods for compensating for non-linearity of a non-linear subsystem using predistortion are disclosed. In one embodiment, a system includes a non-linear subsystem and a predistorter configured to effect predistortion of an input signal of the non-linear subsystem such that the predistortion compensates for a non-linear characteristic of the non-linear subsystem. In addition, the system includes a narrowband filter that filters a feedback signal that is representative of an output signal of the non-linear subsystem to provide a filtered feedback signal, and an adaptor that adaptively configures the predistorter based on the filtered feedback signal and a reference signal that is representative of an input signal of the non-linear subsystem. By utilizing the filtered feedback signal, rather than the feedback signal, a complexity, and therefore, cost of the adaptor is substantially reduced.

This invention aims to present a smart and dynamic power amplifier module that features both power combining and power sharing capabilities. The proposed flexible power amplifier (PA) module consists of a pre-processor, N PAs, and a post-processor. The pre-processor is an M-to-N wavefront (WF) multiplexer (muxer), while the post processor is a N-to-M WF de-multiplexer (demuxer), where N≧M≧2. Multiple independent signals can be concurrently amplified by a proposed multi-channel PA module with a fixed total power output, while individual signal channel outputs feature different power intensities with no signal couplings among the individual signals. In addition to basic configurations, some modules can be configured to feature both functions of parallel power amplifiers and also as M-to-M switches. Other programmable features include configurations of power combining and power redistribution functions with a prescribed amplitude and phase distributions, as well as high power PA with a linearizer.

A multichannel transmission system which includes a calibration functionality that allows precise calibration of the frequency conversion chains and of the multiport amplifier of the system to be performed without interruption of service. The proposed calibration makes it possible to correct the defects over the entire frequency band of the system.

Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p.sub.1, p.sub.2, . . . , p.sub.k} and a second set of values {s.sub.1, s.sub.2, . . . , s.sub.k} that represent a LUT value of s.sub.1.Math.2.sup.p.sup.1+s.sub.2.Math.2.sup.p.sup.2+ . . . +s.sub.k.Math.2.sup.p.sup.k where each value s.sub.i ∈{+1 , −1} where k≥2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p.sub.1, p.sub.2, . . . , p.sub.k} and {s.sub.1, s.sub.2, . . . , s.sub.k} to provide an output sample.