A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

A low drop-out (LDO) voltage regulator circuit includes a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node. A current regulation loop senses current flowing through the power transistor and modulates the control signal to cause the power transistor to output a constant current to the output node. A voltage regulation loop senses voltage at the output node and modulates the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated. The current regulation loop includes a bipolar transistor connected to the control terminal of the power transistor, where a base terminal of the bipolar transistor is driven by a signal dependent on a difference between the sensed current flowing through the power transistor and a reference.

The disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as long term evolution (LTE). An operation method of a device for upconversion in a wireless communication system is provided. The method includes receiving a first local oscillator (LO) signal, generating a second LO signal, based on the first LO signal and cross-coupled latches, receiving an input signal, generating an upconverted frequency, based on the second LO signal and the input signal, generating an output signal obtained by processing a harmonic component included in the upconverted frequency, and transmitting the generated output signal.

A low drop-out (LDO) voltage regulator circuit includes a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node. A current regulation loop senses current flowing through the power transistor and modulates the control signal to cause the power transistor to output a constant current to the output node. A voltage regulation loop senses voltage at the output node and modulates the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated. The current regulation loop includes a bipolar transistor connected to the control terminal of the power transistor, where a base terminal of the bipolar transistor is driven by a signal dependent on a difference between the sensed current flowing through the power transistor and a reference.

A circuit for increasing an output direct-current level of a transimpedance amplification stage in a TIA (Trans-Impedance Amplifier) includes a transimpedance amplification stage, a differential amplification stage, a level boosting unit, and a DC-restore loop. An input terminal of the transimpedance amplification stage is used for inputting a photocurrent signal. An output terminal of the transimpedance amplification stage is directly connected to an input terminal of the differential amplification stage.

A wireless electric field power transmission system comprises: a transmitter comprising a transmitter antenna, the transmitter antenna comprising at least two conductors defining a volume therebetween; and at least one receiver, wherein the transmitter antenna transfers power wirelessly via electric field coupling when the at least one receiver is within the volume.

A composite transconductance amplifier is formed using a single transconductance amplifier with its output connected to a load via one or more resistors in series. The single transconductance amplifier has a linear transconductance (gm). As the current through the series resistors is increased, the voltage drops across the nodes of the resistors increase. Control terminals of separate drive circuits are connected to the various nodes and successively turn on as the current from the single transconductance amplifier slews more positive. Thus, the effective gm of the composite transconductance amplifier is based on the gm of the single transconductance amplifier and the currents contributed by the successively enabled drive circuits. Therefore, the gm is nonlinear. Pull-down drive circuits are also connected to the resistor nodes to successively pull down the current as the output from the single transconductance amplifier slews negative. The composite transconductance amplifier has low quiescent current.

An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit with at least one push-pull amplifier, wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal of a push-pull amplifier with an applied test signal and a second output signal of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio.

An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.

An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.