An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

A differential residue amplifier fits between Analog-to-Digital Converter (ADC) stages. Switched-Capacitor Common-Mode Feedback circuits determine voltage shifts. An AC-coupled input network uses switched capacitors to shift upward voltages of the differential inputs to the residue amplifier to apply to an upper pair of p-channel differential transistors with sources connected to the power supply. The AC-coupled input network also shifts downward in voltage the differential inputs to the residue amplifier to apply to a lower pair of n-channel differential transistors with grounded sources. The drains of the p-channel differential transistors connect to differential outputs through p-channel cascode transistors. N-channel cascode transistors connect the drains of the n-channel differential transistors to the differential outputs. The drains of differential transistors can be input to differential amplifiers to drive the gates of the cascode transistors for gain boosting. No tail current is used, allowing for wider output-voltage swings with low supply voltages.

A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

Chopper amplifiers with high pass filters for suppressing chopping ripple are provided herein. In certain embodiments, a chopper amplifier includes an input chopping circuit, an amplification circuit, a low frequency content detection circuit, and an output chopping circuit electrically connected in a cascade. The low frequency content detection circuit operates in combination with a transconductance or other gain circuit as a high pass filter that filters input offset voltage and/or low frequency noise of the amplification circuit, thereby suppressing output chopping ripple from arising.

An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.

A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

Chopper amplifiers with high pass filters for suppressing chopping ripple are provided herein. In certain embodiments, a chopper amplifier includes an input chopping circuit, an amplification circuit, a low frequency content detection circuit, and an output chopping circuit electrically connected in a cascade. The low frequency content detection circuit operates in combination with a transconductance or other gain circuit as a high pass filter that filters input offset voltage and/or low frequency noise of the amplification circuit, thereby suppressing output chopping ripple from arising.

An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.