A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.

Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.

A fully differential amplifier includes: an input stage comprising a first amplification circuit and a second amplification circuit, one of which is configured to generate a push signal and the other of which is configured to generate a pull signal, each by amplifying a differential input signal; an output stage for generating a differential output signal based on the push signal and the pull signal; and a feedback circuit for providing common mode feedback to the first amplification circuit based on the differential output signal, wherein the second amplification circuit may include a passive network for setting a common mode voltage of the push signal or the pull signal.

In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.

Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.

Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.

A differential amplifier circuit includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generate a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series between the drain and the source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between the gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.

An amplifier includes an amplifier circuit and a gain adjusting circuit. The amplifier circuit has a design gain and a real gain and is configured to output an output signal according to an input signal and the real gain. The gain adjusting circuit is coupled to the amplifier circuit and is configured to receive the input signal to compare a voltage of the input signal with a first reference voltage, wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjusting circuit increases the real gain of the amplifier circuit, so that the real gain approach the design gain.

An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.