An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.

An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.

An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.

A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.

Provided is a power amplifier installed in wireless communication terminals and systems. According to one aspect of the present invention, a reconfigurable power amplifier capable of selecting a wide band frequency is provided. The reconfigurable power amplifier includes input transistors receiving a radio frequency (RF) signal and a reconfigurable adaptive power cell configured to select the wide band frequency by applying a common-gate bias voltage to a plurality of common-gate transistors with a plurality of separate common gates to amplify the RF signal.

According to one exemplary embodiment, a chip is described, comprising a plurality of cascode circuits, wherein each cascode circuit has at least one cascode having at least one respective cascode transistor, a voltage generation circuit which is set up to generate control voltages for controlling the cascode transistors of the cascode circuits, a respective transistor circuit for each cascode, which is connected between the voltage generation circuit and the cascode, has a respective source follower and is set up to generate a cascode transistor control voltage for the at least one cascode transistor of the cascode by means of the respective source follower from a respective control voltage of the control voltages generated by the voltage generation circuit.