An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

A chopper-stabilized amplifier includes a first transconductance amplifier and a first chopper circuit coupled to an input of the first transconductance amplifier. A second chopper circuit is coupled to an output of the first transconductance amplifier. The chopper-stabilized amplifier also includes second and third transconductance amplifiers having inputs coupled to the output of the first transconductance amplifier. The second transconductance amplifier produces an output responsive to a first notch clock signal having a first phase relative to the chopping of the second chopper circuit. The third transconductance amplifier produces an output responsive to a second notch clock signal having a second phase relative to the first phase. The output signals produced by the second and third transconductance amplifiers are added to filter ripple noise at the outputs of the second and third transconductance amplifiers.

A magnetic operational amplifier having a differential stage includes a first magnetic field effect transistor MAGFET and a differential signal conditioner, the differential signal conditioner including a load stage, a differential input pair connected to the load stage and a biasing current source connected to the differential input pair; the magnetic field effect transistor MAGFET being connected to the load stage as a second differential input pair and the differential signal conditioner including a second biasing current source connected to the magnetic field effect transistor MAGFET.

A chopper-stabilized amplifier includes a first transconductance amplifier and a first chopper circuit coupled to an input of the first transconductance amplifier. A second chopper circuit is coupled to an output of the first transconductance amplifier. The chopper-stabilized amplifier also includes second and third transconductance amplifiers having inputs coupled to the output of the first transconductance amplifier. The second transconductance amplifier produces an output responsive to a first notch clock signal having a first phase relative to the chopping of the second chopper circuit. The third transconductance amplifier produces an output responsive to a second notch clock signal having a second phase relative to the first phase. The output signals produced by the second and third transconductance amplifiers are added to filter ripple noise at the outputs of the second and third transconductance amplifiers.

A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit. The feedback circuit is configured to feed the selected output back to the differential amplifier circuit.

A magnetic operational amplifier having a differential stage includes a first magnetic field effect transistor MAGFET and a differential signal conditioner, the differential signal conditioner including a load stage, a differential input pair connected to the load stage and a biasing current source connected to the differential input pair; the magnetic field effect transistor MAGFET being connected to the load stage as a second differential input pair and the differential signal conditioner including a second biasing current source connected to the magnetic field effect transistor MAGFET.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit. The feedback circuit is configured to feed the selected output back to the differential amplifier circuit.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.