The present disclosure provides a differential input circuit. The differential input circuit includes: a P-channel FET differential input pair; an N-channel FET differential input pair; a first power line configured to receive a first voltage; a second power line configured to receive a second voltage lower than the first voltage; a first P-channel FET; a constant current source (CS1) disposed between the first power supply line and the P-channel FET differential input pair as well as the first P-channel FET; a current mirror circuit disposed between the first P-channel FET as well as the N-channel FET differential input pair and the second power supply line; and a logic circuit configured to supply a binarized logic signal to a gate of the first P-channel FET.

A field effect transistor (FET) transconductance device with varying gate lengths is disclosed. In one aspect, the varying effective gate lengths are used in a differential architecture to obtain linear even and odd order operation simultaneously. In a particular aspect, the effective gate lengths may be varied according to a differential Multi-Tanh-like architecture. This variation of effective gate lengths enables a compact implementation particularly as compared to varying gate width or emitter areas while also providing linear even and odd order operation simultaneously.

A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate.

A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate.