A first amplifier circuit includes differential pair transistors that amplify a difference between input voltages and active load transistors connected to the differential pair transistors. A second amplifier circuit amplifies output voltage of the first amplifier circuit. An offset correction current source is connected in parallel with the active load transistors and adjusts electric current flowing through the differential pair transistors to correct offset voltage. An offset correction switch switches a driving state of the offset correction current source. A transconductance proportional current generation circuit generates transconductance proportional current for compensating for temperature drift of offset correction voltage for correcting the offset voltage. The transconductance proportional current is proportional to trans conductance.

The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.

The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.

Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

A voltage regulator and a power supply are provided. The voltage regulator includes an operational amplifier and an offset voltage control module. The offset voltage control module includes one or more stages of regulation branches connected in parallel, and controls an offset voltage of the operational amplifier with the one or more stages of regulation branches to regulate the output voltage. The offset voltage control module also includes a bandgap reference generation circuit, configured to generate a reference voltage irrelevant to a temperature coefficient that is received by the operational amplifier from the input terminal, wherein the bandgap reference generation circuit comprises at least one of: a V.sub.GS-based bandgap reference generation circuit having a full CMOS reference offset structure, a PTAT unit-based and V.sub.GS-based bandgap reference generation circuit having a full CMOS reference offset structure, and a PTAT unit-based and BJT-based bandgap reference generation circuit having a complementary structure.

Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

A voltage regulator and a power supply are provided. The voltage regulator includes an operational amplifier and an offset voltage control module. The offset voltage control module includes one or more stages of regulation branches connected in parallel, and controls an offset voltage of the operational amplifier with the one or more stages of regulation branches to regulate the output voltage. The offset voltage control module also includes a bandgap reference generation circuit, configured to generate a reference voltage irrelevant to a temperature coefficient that is received by the operational amplifier from the input terminal, wherein the bandgap reference generation circuit comprises at least one of: a V.sub.GS-based bandgap reference generation circuit having a full CMOS reference offset structure, a PTAT unit-based and V.sub.GS-based bandgap reference generation circuit having a full CMOS reference offset structure, and a PTAT unit-based and BJT-based bandgap reference generation circuit having a complementary structure.

A voltage regulator and a power supply are provided. The voltage regulator includes an operational amplifier and an offset voltage control module. The operational amplifier includes an input terminal and an output terminal, and is configured to generate an output voltage to be output from the output terminal based on a reference voltage received from the input terminal. The offset voltage control module includes one stage of regulation branch or more stages of regulation branches connected in parallel, and is configured to control an offset voltage of the operational amplifier based on selection of the regulation branch to regulate the output voltage. Since sine each stage of regulation branch in the offset voltage control module is based on a transistor structure, as compared with the voltage dividing resistor in the related art, the transistor has lower power consumption, and thus power consumption of the voltage regulator is lowered.

Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.