A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit amplifies a voltage difference between its input terminals, to generate plural pre-stage transconductance currents flowing through corresponding plural pre-stage transconductance nodes. The floating control circuit includes: a floating reference transistor configured as a source follower and a floating amplifier. The floating amplifier and the floating reference transistor are coupled to form feedback control and to generate an upper driving signal and a lower driving signal according to a floating reference level in the floating control circuit. The upper driving signal is higher than the lower driving signal with a predetermined voltage difference. The floating control circuit is electrically connected to the plural pre-stage transconductance nodes and is floating in common mode relative to the pre-stage transconductance nodes.

A pipelined SAR ADC includes a first stage and passive residue transfer is used to boost a conversion speed. Owing to the passive residue transfer, the first stage may be released during a residue amplification phase, cutting down a large part of the first-stage timing budget. An asynchronous timing scheme may also be adopted in both the first- and second-stage SAR ADCs to maximize the overall conversion speed. Lastly, a dynamic amplifier with proposed PVT stabilization technique may be employed to further save power consumption and improve the conversion speed simultaneously.

An amplifier device and a duplexer circuit are provided. The amplifier device includes a first differential amplifier circuit and a controller. The first differential amplifier circuit includes first and second radio frequency (RF) input terminals, first and second transistors, first and second adjustable capacitor circuits, and first and second RF output terminals. The controller adjusts capacitance values of the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of a characteristic related to a first RF input signal of the first differential amplifier circuit, a characteristic related to the second RF input signal of the first differential amplifier circuit, a matching deviation between the first transistor and the second transistor of the first differential amplifier circuit, and a characteristic of the amplifier device.

Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.

A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit amplifies a voltage difference between its input terminals, to generate plural pre-stage transconductance currents flowing through corresponding plural pre-stage transconductance nodes. The floating control circuit includes: a floating reference transistor configured as a source follower and a floating amplifier. The floating amplifier and the floating reference transistor are coupled to form feedback control and to generate an upper driving signal and a lower driving signal according to a floating reference level in the floating control circuit. The upper driving signal is higher than the lower driving signal with a predetermined voltage difference. The floating control circuit is electrically connected to the plural pre-stage transconductance nodes and is floating in common mode relative to the pre-stage transconductance nodes.

An amplifier device and a duplexer circuit are provided. The amplifier device includes a first differential amplifier circuit and a controller. The first differential amplifier circuit includes first and second radio frequency (RF) input terminals, first and second transistors, first and second adjustable capacitor circuits, and first and second RF output terminals. The controller adjusts capacitance values of the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of a characteristic related to a first RF input signal of the first differential amplifier circuit, a characteristic related to the second RF input signal of the first differential amplifier circuit, a matching deviation between the first transistor and the second transistor of the first differential amplifier circuit, and a characteristic of the amplifier device.

The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

A method and apparatus for correcting baseline wander is disclosed. The method and apparatus may include generating filtered signals by filtering input signals using a filter circuit. An equalizer circuit using the filtered signals may generate output signals. Feedback networks may be configured to couple a respective output signal to a corresponding filtered signal.

Apparatus and methods for power amplifiers isolated by differential ground are provided. In certain implementations, a mobile device includes a transceiver that generates a plurality of radio frequency input signals including a first radio frequency input signal and a second radio frequency input signal, and a plurality of differential power amplifiers including a first differential power amplifier that provides amplification to the first radio frequency input signal and a second differential power amplifier that provides amplification to the second radio frequency input signal. The first differential power amplifier and the second differential power amplifier each operate with differential ground so as to provide isolation between the first differential power amplifier and the second differential power amplifier.

A circuit for implementing an operational transconductance amplifier (OTA) based on telescopic topology, wherein cascode transistors of the operational transconductance amplifier (OTA) are self-biased without using additional biasing circuitry, which not only reduces power consumption but also achieves high gain without extra current, and each cascode stage of the OTA has a pair of transistors so that the swing of the output differential signals of the OTA can be completely symmetrical so as to benefit second-order harmonic rejection, CMRR and PSRR.