Certain aspects of the present disclosure provide methods and apparatus for implementing an amplification system. The amplification system includes an amplifier comprising differential inputs and an output. The differential inputs include an inverting input and a non-inverting input. The amplification system further includes a feedback path from the output coupled to the inverting input. The feedback path from the output is coupled to at least one of an inverting amplifier or buffer, and the at least one of the inverting amplifier or buffer is further coupled to the non-inverting input.

Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.

Radio Frequency (RF) amplifier design with RFIC suffers gain variations from gain variations due to wafer process variations, temperature changes, and supply voltage changes. Three methods are proposed to achieve constant amplifier gain, either through on-chip wafer calibration, or self-calibration. Through automatic adjustment of amplifier bias current, the proposed methods maintain constant amplifier gain over process, temperature, supply voltage variations. Under the proposed Method 1, a constant transconductance Gm with enhanced gain accuracy is maintained via wafer calibration. Under the proposed Method 2, a constant transconductance Gm is maintained by time-domain averaging through different transistors. Under the proposed Method 3, a constant Gm*R or RF gain is maintained considering the impedance of a matching network of the RF amplifier.

A circuit includes a first transconductance stage having an output. The circuit further includes an output transconductance stage, and a first source-degenerated transistor having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage.

A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

A differential residue amplifier fits between Analog-to-Digital Converter (ADC) stages. Switched-Capacitor Common-Mode Feedback circuits determine voltage shifts. An AC-coupled input network uses switched capacitors to shift upward voltages of the differential inputs to the residue amplifier to apply to an upper pair of p-channel differential transistors with sources connected to the power supply. The AC-coupled input network also shifts downward in voltage the differential inputs to the residue amplifier to apply to a lower pair of n-channel differential transistors with grounded sources. The drains of the p-channel differential transistors connect to differential outputs through p-channel cascode transistors. N-channel cascode transistors connect the drains of the n-channel differential transistors to the differential outputs. The drains of differential transistors can be input to differential amplifiers to drive the gates of the cascode transistors for gain boosting. No tail current is used, allowing for wider output-voltage swings with low supply voltages.

Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.

A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation. In one aspect, active resistors are used in order to compensate for temperature variations.