A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.

An operational amplifier operates in the entire voltage range of supplied first and second voltages as an input and output range. An active load is formed with a field-effect transistor of a first conductivity type. First and second differential pairs are formed with a field-effect transistor of a second conductivity type. The first differential pair is configured such that differential amplification is possible when an input voltage is the second voltage, and the second differential pair is configured such that differential amplification is possible when the input voltage is the first voltage. A selection circuit selectively connects one of the first and second differential pairs to the active load through a differential node in accordance with the input voltage.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

A comparator having: a first transistor coupled to a first input terminal; a first current source coupled to the first transistor; a second transistor coupled to a second input terminal and coupled to the first current source; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in series with the first transistor; a sixth transistor coupled in series with the second transistor; a seventh transistor coupled to the first input terminal and coupled as a source follower to the fifth transistor; and an eighth transistor coupled to the second input terminal and coupled as a source follower to the sixth transistor. The comparator also including a differential amplifier coupled to the first output terminal and coupled to the second output terminal.

Embodiments of a linear equalizer are disclosed. In an embodiment, a linear equalizer includes a plurality of input transistors, a plurality of gain control transistors and first and second impedance elements. The plurality of input transistors is connected to input terminals of the linear equalizer to receive input signals. The plurality of gain control transistors is connected between a supply voltage and the plurality of input transistors. The plurality of gain control transistors is also connected to gain control terminals to receive gain control signals. At least some of the gain control transistors are connected to output terminals of the linear equalizer to transmit output signals. The first and second impedance elements are connected between at least some of the input transistors and at least one fixed voltage. A peaking gain of the linear equalizer is defined by gain control signals applied to the gain control terminals.

An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

A voltage generation circuit includes a driver configured to generate an internal voltage by driving an external voltage depending on a driving signal; an amplifier configured to generate the driving signal depending on a result of comparing a reference voltage and a feedback voltage; and a switch configured to delay a decrease of the internal voltage by precharging a node of the amplifier with a predetermined voltage depending on a control signal.

An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.

A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.