Systems and method for improving operation of a radio frequency system are provided. One embodiment includes a switching power amplifier that outputs an amplified analog electrical signal based on an input electrical signal and voltage of an envelope voltage supply rail. The switching power amplifier includes a first transistor with a gate that receives the input electrical signal, a source electrically coupled to the envelope voltage supply rail, and a drain electrically coupled to an output of the switching power amplifier; a second transistor with a gate that receives the input electrical signal, a source electrically coupled to ground, and a drain electrically coupled to the output; and a third transistor with a gate that receives the input electrical signal, a drain electrically coupled to the envelope voltage supply rail, and a source electrically coupled to an output of another switching power amplifier.

A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

A voltage generation circuit includes a driver configured to generate an internal voltage by driving an external voltage depending on a driving signal; an amplifier configured to generate the driving signal depending on a result of comparing a reference voltage and a feedback voltage; and a switch configured to delay a decrease of the internal voltage by precharging a node of the amplifier with a predetermined voltage depending on a control signal.

A transconductor circuitry (10) with adaptive biasing comprises a first input terminal (ElOa) to apply a first input signal (inp), and a second input terminal (ElOb) to apply a second input signal (inn). A control circuit (200) is configured to control a first controllable current source (110) in a first current path (101) and a second controllable current source (120) in a second current path (102) in response to at least one of a first potential of a first node (N1) of the first current path (101) and a second potential of a second node (N2) of the second current path (102). The first node (N1) is located between a first transistor (150) and the first controllable current source (110), and the second node (N2) is located between a second transistor (160) and the second controllable current source (120).

An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

A high-linearity dynamic amplifier includes a first differential branch and a second differential branch. The first differential branch includes a first MOS transistor and a second MOS transistor which are connected between a high-level terminal and a ground-level terminal in series. A connection point of the first MOS transistor and the second MOS transistor is a second output terminal. The second differential branch includes a third MOS transistor and a fourth MOS transistor which are connected between the high-level terminal and the ground-level terminal in series. A connection point of the third MOS transistor and the fourth MOS transistor is a first output terminal. A grid terminal of the second MOS transistor is connected to a drain terminal of the fourth MOS transistor. A grid terminal of the fourth MOS transistor is connected to a drain terminal of the second MOS transistor.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

A differential feedback circuit with an active noise cancelation technique using a dual input differential pair. In the differential feedback circuit, a feedback voltage and a reference voltage connect to a primary input pair. Sensed noise at the inputs is put to a secondary input pair of the differential amplifier, which is inverted with respect to the primary input pair. In other words, the reference voltage, which may be subject to noise, connects directly to one terminal of the secondary input pair and through a low-pass filter to another terminal of the secondary input pair so that the noise, which may be coupled to the differential feedback circuit, cancels at the output of the differential feedback circuit.