Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.

The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.

An apparatus, such as a coherent optical receiver, includes a TIA, the TIA including a cascode circuit having a cascode node. A first tunable element is connected to tunably shunt the cascode node to vary a voltage gain of the TIA, e.g., up to a first amount. Implementations of the TIA further include another tunable element connected to vary a load of the cascode circuit to vary the voltage gain, e.g., up to a second amount. A current steering circuit may be provided to vary the voltage gain up to a third amount, each of the amounts being only a fraction of a target voltage gain variation of the TIA.

A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.

A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.

Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.