A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.

A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.

A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.

A digital to analog converter (DAC) can include a current mode DAC to receive an OC word from digital logic indicating an amount of current to add to or remove from sources of respective transistors of an amplifier and generate a current based on the OC word, an active output stage including a positive current mirror and a negative current mirror to generate a positive current and a negative current based on at least a portion of the generated current, and a plurality of outputs including a plurality of sink outputs and a plurality of source outputs to provide the positive and negative currents to the sources of the respective transistors.

An amplification circuit with a common-mode voltage compensation circuit is shown. The common-mode voltage compensation circuit has a first compensation resistor coupled between an input terminal of a loop filter of the amplification circuit and a control node, and a second compensation resistor coupled between another input terminal of the loop filter and the control node. The control node is coupled to a power ground voltage when the two output signals of the amplification circuit are high, and it is coupled to a power supply voltage when the two output signals of the amplification circuit are low.

A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.

A digital to analog converter (DAC) can include a current mode DAC to receive an OC word from digital logic indicating an amount of current to add to or remove from sources of respective transistors of an amplifier and generate a current based on the OC word, an active output stage including a positive current mirror and a negative current mirror to generate a positive current and a negative current based on at least a portion of the generated current, and a plurality of outputs including a plurality of sink outputs and a plurality of source outputs to provide the positive and negative currents to the sources of the respective transistors.

A dynamic common reference input (CMRI) signal may be provided to an operational amplifier, or op-amp, in an amplifier system to reduce the common mode ripple of the fully-differential op-amp, while adding little or no noise in the amplifier system. The dynamic CMRI signal may be controlled such that a common-mode component of two amplifier input nodes of the operational amplifier is made approximately independent of two input signals received at two system input nodes of the amplifier system. An amplifier system with the dynamic CMRI may be used in class-D amplifiers, such as amplifiers for audio systems that generate output for headphones or speakers.

A class-D amplifier includes a loop filter, a pulse-width modulation (PWM) circuit, an output circuit, and a common-mode control circuit. The loop filter receives an input signal of the class-D amplifier to generate a filtered signal. The PWM circuit converts a non-PWM signal into a PWM signal, wherein the non-PWM signal is derived from at least the filtered signal. The output circuit generates an output signal of the class-D amplifier according to the PWM signal. The common-mode control circuit monitors a common-mode level of the output signal to generate a common-mode control signal for PWM common-mode control.

A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.