A differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.

An internal voltage offset between a positive input and a negative input of a first operational amplifier is compensated. The negative input and the positive input of the first operational amplifier are coupled at the same voltage level. A comparison current generated at an output of the first operational amplifier has a sign that is representative of a sign of the internal voltage offset. The output of the first operational amplifier is biased to a threshold voltage using a current-to-voltage converter. A control voltage is generated from a sum of the threshold voltage and a voltage conversion of the comparison current. Compensation for the internal voltage offset between the positive and negative inputs of the first operational amplifier is made dependent on the control voltage.

In an embodiment a differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.

A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

A high gain differential amplifier includes first through eighth transistors, first through third degeneration resistors, and first through third current sources. The fourth and fifth transistors form a p-type metal-oxide-semiconductor (PMOS) transistor pair. Further, the second and eighth transistors form a current mirror circuit. The PMOS transistor pair and the current mirror circuit form a common mode feedback circuit. The high gain differential amplifier controls the common-mode output voltage with the common mode feedback circuit and a reference voltage.

A high gain differential amplifier includes first through eighth transistors, first through third degeneration resistors, and first through third current sources. The fourth and fifth transistors form a p-type metal-oxide-semiconductor (PMOS) transistor pair. Further, the second and eighth transistors form a current mirror circuit. The PMOS transistor pair and the current mirror circuit form a common mode feedback circuit. The high gain differential amplifier controls the common-mode output voltage with the common mode feedback circuit and a reference voltage.