H03F2203/45522

Semiconductor device

According to one embodiment, a semiconductor device includes the following configuration. A detection circuit detects a state of a clock signal. An amplification circuit changes a gain based on the state of the clock signal detected by the detection circuit. An amplification circuit amplifies a first voltage with the gain and outputs a second voltage obtained as a result of amplification. A conversion circuit converts the second voltage output from the amplification circuit to first data. An isolation circuit includes a driver and a receiver electrically isolated from the driver. The driver transmits a signal corresponding to the first data to the receiver. The receiver outputs second data corresponding to the signal transmitted from the driver. The output circuit outputs the second data output from the isolation circuit.

Voltage-to-current architecture and error correction schemes

Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

Programmable gain amplifier and a delta sigma analog-to-digital converter containing the PGA
11522554 · 2022-12-06 · ·

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

SEMICONDUCTOR CIRCUIT
20230089685 · 2023-03-23 ·

According to one embodiment, a semiconductor circuit includes a first transimpedance amplifier and a second transimpedance amplifier. The first transimpedance amplifier is configured to convert an input current to a first output voltage and output the first output voltage from a first output terminal when a reference voltage is supplied to a first input terminal and the input current is supplied to a second input terminal. The second transimpedance amplifier has a circuit configuration similar to a circuit configuration of the first transimpedance amplifier. The second transimpedance amplifier is configured to output a second output voltage from a second output terminal when the reference voltage is supplied to a third input terminal.

Circuitry applied to multiple power domains

The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.

Multi-channel cinema amplifier with power-sharing, messaging and multi-phase power supply

An integrated cinema amplifier comprises a power supply stage that distributes power over a plurality of channels for rendering immersive audio content in a surround sound listening environment. The amplifier automatically detects maximum and net power availability and requirements based on audio content by decoding audio metadata and dynamically adjusts gains to each channel or sets of channels based on content and operational/environmental conditions. A power supply stage provides power to drive a plurality of channels corresponding to speaker feeds to a plurality of speakers. The amplifier has a front panel having an LED array with each LED associated with a respective channel or group of channels of the multi-channel amplifier, and a control unit configured to light the LEDs according to display patterns based on operating status or error conditions of the amplifier.

Method for improving die area and power efficiency in high dynamic range digital microphones
11637537 · 2023-04-25 · ·

Exemplary multipath digital microphones described herein can comprise exemplary embodiments of automatic gain control and multipath digital audio signal digital signal processing chains, which allow low power and die size to be achieved as described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can facilitate switching between multipath digital audio signal digital signal processing chains while minimizing audible artifacts associated with either the change in the gain automatic gain control amplifiers switching between multipath digital audio signal digital signal processing chains.

Amplifier compensation circuits and methods
11664772 · 2023-05-30 · ·

Various examples are directed to a frequency-compensated amplifier circuit comprising a first multi-stage amplifier comprising a first amplifier input node, a first amplifier output node, and a first amplifier intermediate node. A first feedback path between the first amplifier input node and the first amplifier output node comprises a feedback resistance. A second feedback path between the first amplifier output node and the first amplifier intermediate node comprises a first capacitor and a portion of the feedback resistance. A first switch circuit may be electrically coupled to the first capacitor and to the feedback resistance. The first switch circuit may have a first state in which the first capacitor is coupled to a first tap point of the feedback resistance and the portion of the feedback resistance has a first value. The first switch circuit may also have a second state in which the first capacitor is coupled to a second tap point of the feedback resistance and the portion of the feedback resistance has a second value different than the first value.

PROGRAMMABLE GAIN AMPLIFIER AND A DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER CONTAINING THE PGA
20230110204 · 2023-04-13 · ·

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

SEMICONDUCTOR DEVICE
20230155561 · 2023-05-18 ·

According to one embodiment, a semiconductor device includes the following configuration. A detection circuit detects a state of a clock signal. An amplification circuit changes a gain based on the state of the clock signal detected by the detection circuit. An amplification circuit amplifies a first voltage with the gain and outputs a second voltage obtained as a result of amplification. A conversion circuit converts the second voltage output from the amplification circuit to first data. An isolation circuit includes a driver and a receiver electrically isolated from the driver. The driver transmits a signal corresponding to the first data to the receiver. The receiver outputs second data corresponding to the signal transmitted from the driver. The output circuit outputs the second data output from the isolation circuit.