An isolation amplification circuit having an input stage circuitry and a control circuitry stage interconnected through a galvanic isolation barrier. The input stage circuitry includes a first filter network and a second filter network for supplying first and second output signals in response to the application of first and second electrical input signals. The input stage circuitry includes a first feedback path configured for applying a first feedback signal to a common node of the first filter network to close a first feedback loop around the first filter network and a second feedback path configured for applying a second feedback signal to a common node of the second filter network to close a second feedback loop around the second filter network.

An amplifier circuit includes a potential relation between a common emitter amplifier circuit (amplifier circuit body) including an NPN transistor (bipolar transistor) and a clamp circuit which maintains a potential relation between a base-collector of the NPN transistor of the common emitter amplifier circuit. The clamp circuit includes a level shift circuit and a clamp diode for suppressing a decrease in the collector potential of the NPN transistor of the common emitter amplifier circuit.

An isolation amplification circuit having an input stage circuitry and a control circuitry stage interconnected through a galvanic isolation barrier. The input stage circuitry includes a first filter network and a second filter network for supplying first and second output signals in response to the application of first and second electrical input signals. The input stage circuitry includes a first feedback path configured for applying a first feedback signal to a common node of the first filter network to close a first feedback loop around the first filter network and a second feedback path configured for applying a second feedback signal to a common node of the second filter network to close a second feedback loop around the second filter network.

In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.

An amplifier circuit includes a potential relation between a common emitter amplifier circuit (amplifier circuit body) including an NPN transistor (bipolar transistor) and a clamp circuit which maintains a potential relation between a base-collector of the NPN transistor of the common emitter amplifier circuit. The clamp circuit includes a level shift circuit and a clamp diode for suppressing a decrease in the collector potential of the NPN transistor of the common emitter amplifier circuit.

In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.

In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.

In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.

A system includes a monitored component and a comparator configured to compare a sense voltage from the monitored component with a reference voltage. The system also includes an adaptive input clamping circuit configured to limit the sense voltage input to the comparator to below an upper threshold voltage.

A circuit for amplifying signals from a Micro Electro-Mechanical System (MEMS) capacitive sensor is provided. First and second input nodes receive a sensing signal applied differentially between the input nodes. A first amplifier stage and a second amplifier stage, respectively, produce a differential output signal between first and second output nodes. A common mode signal is detected at the output nodes. A voltage divider having an intermediate tap node is coupled between the first output node and the second output node. A feedback stage is coupled between the intermediate tap node of the voltage divider and the inputs of the first amplifier stage and the second amplifier stage, where the feedback line is sensitive to the common mode signal at the output nodes.