The application discloses a tuner and a method for tuning a signal. The tuner comprises: a sampling module, the sampling module being configured to receive an input signal and a set of control signals, sample the input signal under the control of the set of control signals and generate a sample signal; wherein each of the set of control signals has a control period equal to (N*T.sub.VCO), and the control periods of the set of control signals synchronize with each other; a set of weighting modules, wherein each of the set of weighting modules is configured to receive the set of sample signals and weight the received sample signals with a group of weighting factors to generate a group of weighted signals; and one or more summing modules, each summing module being configured to receive one group of weighted signals generated by one of the set of weighting modules and sum the group of weighted signals to output an output signal, wherein the output signal is the input signal being shifted by a predefined frequency f.sub.VCO*m.sub.k/N.

A preamplifier amplifies signals input to first and second input terminals. A first switching circuit receives first and second input signals and outputs those to the first and second input terminals. A switched capacitor circuit samples two signals amplified by the preamplifier. Differential signals sampled by the switched capacitor circuit are respectively input to third and fourth input terminals of an integration circuit, and the integration circuit outputs differential signals obtained by those input signals to first and second output terminals. A second switching circuit switches a connection relationship between the switched capacitor circuit and the integration circuit. Each time the cycle changes, the first and second switching circuits switch the connection relationships to cause the signals amplified by the preamplifier to be sampled by double correlation sampling.

A system that utilizes an amplified signal is disclosed that includes a plurality of first switches coupled to a plurality of first impedances. A plurality of second switches coupled to a plurality of second impedances. An amplifier having a first input coupled to the plurality of first switches and a second input coupled to the plurality of second switches. A leakage current offset source coupled to the first input of the amplifier, wherein the leakage current offset source cancels a leakage current component of a first current provided from the plurality of first switches to the first input.

Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.

The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

A current sense amplifier circuit of a circuit device includes: an operational amplifier; a first resistor provided between one end of a shunt resistor and a first node, a first switch provided between the first node and a first input node, a second resistor provided between another end of the shunt resistor and a second node, a second switch provided between the second node and a second input node, a third resistor provided between a constant voltage node and the third node, a third switch provided between the third node and the first input node, a fourth resistor provided between the constant voltage node and a fourth node, and a fourth switch provided between the fourth node and the second input node.

An amplifier circuit is capable of switching between a unipolar output voltage domain and a bipolar output voltage domain. The amplifier circuit comprises an operational amplifier with a feedback circuit that is configurable using switches. By controlling the switches, the amplifier's feedback circuit can switched between two different arrangements having a positive and a negative signal gain, respectively. The amplifier circuit is designed such that the noise gain is the same in both operating modes, allowing a single noise compensation approach to be used for both operating modes. Since configurability of the circuit is achieved using static switches, the amplifier circuit maintains high accuracy and experiences no appreciable impact on power consumption as a result of implementing the switching.

The disclosure provides a bias voltage calibration circuit adapted for a signal receiving device. The bias voltage calibration circuit includes a reference voltage generator, a voltage-current converter, and a bias current generator. The reference voltage generator receives a voltage adjustment signal, and adjusts a voltage value of a generated reference voltage according to the voltage adjustment signal. The voltage-current converter is coupled to the reference voltage generator, and converts the reference voltage to generate a reference current. The bias current generator generates a plurality of bias currents according to the reference current, and provides the bias current to an equalization circuit of the signal receiving device in a calibration mode.

An inverted group delay circuit is provided. The inverted group delay circuit can offset a group delay between a pair of signals. In a non-limiting example, the inverted group delay circuit can be configured to offset a group delay (e.g., negative group delay) between a time-variant voltage and a time-variant envelope of an analog signal. More specifically, the inverted group delay circuit can output an inverted time-variant voltage having an opposing phase and time-adjusted relative to the time-variant voltage to thereby offset the group delay between the time-variant voltage and the time-variant envelope. As such, the inverted group delay circuit can be provided in a power management integrated circuit (PMIC) to improve timing alignment between a time-variant voltage(s) and a time-variant analog signal(s) at a power amplifier(s), thus helping to reduce potential amplitude distortion when the analog signal(s) is amplified by the power amplifier(s).