The present application provides a window function processing module including an integrating circuit, configured to receive an integrating input signal, the integrating circuit comprising an operational amplifier; an integrating capacitor, coupled to an output terminal and a first input terminal of the operational amplifier; and an adjustable impedance module, coupled between the first input terminal of the operational amplifier and an integrating input terminal of the integrating circuit, wherein the adjustable impedance module is controlled by at least one control signal to adjust an impedance value of the adjustable impedance module; and a control unit, coupled to the integrating circuit, configured to generate the at least one control signal according to a window function, to adjust the integration gain of the integrating circuit, such that the integrating output signal is related to an operation result of the integrating input signal and the window function.

The present invention provides an amplifier circuit, wherein the amplifier circuit includes an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone cancellation circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between an input node and an output node of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit includes a storage block including a switched-capacitor. The aliasing tone cancellation circuit is coupled between the input terminal of the amplifier circuit and the input node of the amplifier, and configured to generate a signal to cancel or reduce an aliasing tone of the feedback signal according to the input signal.

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

Provided are a semiconductor device and a sensor system capable of achieving improvement of noise resistance. Thus, an output circuit 106a in the semiconductor device includes: input terminals 207n, 207p; and an output terminal 208; an output amplifier 201 connecting the input terminals 207n, 207p to the output terminal 208; a feedback element 203 returning the output terminal 208 to the input terminal 207n; a switching transistor 204; and a resistance element 206. A drain of the switching transistor 204 is connected to the input terminal 207n. The resistance element 206 is provided between a back gate of the switching transistor 204 and a power source Vdd and has impedance of a predetermined value or more for suppressing noise of a predetermined frequency generated at the input terminal 207n.

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

Provided is a semiconductor integrated circuit including a pad Pd1 provided on one end side of a resistive element R1 externally provided, a pad Pd5 provided on a different end side of the resistive element R1; an operation amplifier A1, a signal line L11 wired between an output terminal of the operation amplifier A1 and the pad Pd1, a signal line L21 wired between an inverting input terminal of the operation amplifier A1 and the pad Pd5, a ESD protection element r11 provided to the signal line L11, and a signal line L31, through which a voltage signal of the pad Pd1 is transmitted. The signal line L31 is connected to the pad Pd1.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

A programmable (multistep) resistor attenuator architecture (such as for input to a differential amplifier) provides cancellation for harmonic distortion currents. An attenuation node is coupled: (a) to an input node through R; (b) to a virtual ground through kR and a virtual ground switch Swf with on-resistance Rswf; and (c) to a differential ground through mR and a differential ground switch Swp with on-resistance Rswp. Swp can be sized relative to Swf such that a component Ipnf of Ipn through Rswp and mR to the attenuation node, and branching into kR and Rswf, matches (phase/magnitude), a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node. Harmonic distortion cancelation at the virtual ground can be based on matching switches Swf and Swp and the resistors R, mR, kR, reducing sensitivity to PVT variations, input frequency and amplitude. The attenuator architecture is extendable to multistage configurations.

An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.