The present application discloses a trimming circuit of differential amplifier, wherein an output end of the differential amplifier is coupled to a first input end of the differential amplifier through a first voltage-dividing resistor; a shift voltage is coupled to a second input end of the differential amplifier through a second voltage-dividing resistor; the first voltage-dividing resistor and the second voltage-dividing resistor respectively form a T-shaped resistor network structure; the T-shaped resistor network structure comprises: a k-bit resistive network coupled to a T-shaped node and a reference power supply end, wherein a low n-bits of the k-bit resistive network is an R-2R resistive network, and part of branches are connected in series with at least one trimming resistor, and each trimming resistor is connected in parallel with a switch.

An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.

According to an example aspect of the present invention, there is provided an apparatus for an antenna, comprising, a first power amplifier and a second power amplifier and a common ground between the first power amplifier and the second power amplifier, wherein a Radio Frequency, RF, output of the first power amplifier is coupled to the common ground and a RF output of the second power amplifier is coupled to the common ground.

A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.

An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

An amplifier circuit includes: an input circuit configured to receive an input signal; a load circuit provided in series with the input circuit and including a first variable resistance unit and a second variable resistance unit, a resistance value of the first variable resistance unit being controlled by a digital code, a resistance value of the second variable resistance unit being controlled by an analog control voltage; and a correction circuit including a third variable resistance unit having a circuit configuration corresponding to the first variable resistance unit and a fourth variable resistance unit having a circuit configuration corresponding to the second resistance unit, a resistance value of the third variable resistance unit being controlled by the digital code, a resistance value of the fourth variable resistance unit being controlled by the analog control voltage, the correction circuit being configured correct a resistance value of the load circuit.

An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.