An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

A magnetic operational amplifier having a differential stage includes a first magnetic field effect transistor MAGFET and a differential signal conditioner, the differential signal conditioner including a load stage, a differential input pair connected to the load stage and a biasing current source connected to the differential input pair; the magnetic field effect transistor MAGFET being connected to the load stage as a second differential input pair and the differential signal conditioner including a second biasing current source connected to the magnetic field effect transistor MAGFET.

A magnetic operational amplifier having a differential stage includes a first magnetic field effect transistor MAGFET and a differential signal conditioner, the differential signal conditioner including a load stage, a differential input pair connected to the load stage and a biasing current source connected to the differential input pair; the magnetic field effect transistor MAGFET being connected to the load stage as a second differential input pair and the differential signal conditioner including a second biasing current source connected to the magnetic field effect transistor MAGFET.

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

An operational amplifier-based hysteresis comparator and a chip are provided. The hysteresis comparator includes: an input stage and an amplification stage. The input stage includes: a first input branch and a second input branch, where the first input branch generates a first current based on the first voltage, and the second input branch generates a second current based on the second voltage. The first current is connected with a first input terminal of the amplification stage, and the second current is connected with a second input terminal of the amplification stage. An output terminal of the amplification stage outputs a first level when the first current is greater than the second current, and outputs a second level when the first current is less than the second current. The present disclosure changes the hysteresis voltage generation mode, thereby reducing the instability caused by positive feedback.

In an embodiment, an amplifier circuit includes a second stage that includes a first switch circuit including first and second terminals, a plurality of resistive elements coupled between the first and second terminals of the first switch circuit, and a plurality of switches configured to control an equivalent resistance between the first and second terminals of the first switch circuit. During play mode, the second stage has a gain between the input of the second stage and the output of the second stage of a first value. During a transition from mute mode to play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from a second value to the first value. During a transition from play mode to mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value.