H03F2203/45712

Amplifier with a Converting Circuit with Reduced Intrinsic Time Constant
20220116003 · 2022-04-14 ·

An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

AMPLIFIER CIRCUIT USING VOLTAGE-TO-CURRENT CONVERSION TO ACHIEVE UNITY FEEDBACK FACTOR AND INPUT COMMON-MODE REJECTION FOR LINEAR AMPLIFIER AND ASSOCIATED ENVELOPE TRACKING SUPPLY MODULATOR USING THE SAME
20220045647 · 2022-02-10 · ·

An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.

AMPLIFIER FOR MUSIC SIGNAL AND METHOD OF OUTPUTTING WAVEFORM OF MUSIC SIGNAL

An amplifier and a method of outputting a waveform of a music signal capable of outputting a waveform of a music signal exceeding a power supply voltage is provided. An amplifier includes a power supply, an input terminal for a music signal, an amplifying circuit which amplifies the music signal using the power supply, and a jumping-up circuit which is connected to an output end of the amplifying circuit and outputs a waveform exceeding a voltage value of the power supply.

VIRTUAL RESISTIVE LOAD IN FEEDBACK LOOP DRIVING A PIEZOELECTRIC ACTUATOR
20200350837 · 2020-11-05 · ·

A virtual resistive load feedback circuit for driving a piezoelectric actuator is provided that accounts for a hysteresis error and drift within the movement of the actuator. The circuit may include a voltage divider and charge divider. A voltage monitor signal corresponding to a voltage of a driver signal and a current monitor signal corresponding to a current provided to the amplifier are combined by an operational amplifier and include electrical characteristics of the actuator such that the circuit approximates a virtual load across the actuator. A feedback portion of the operational amplifier may include a resistor and capacitor connected in parallel to provide the voltage and charge divide functions. The use of the virtual resistive circuit allows for the piezoelectric actuator to be ground referenced, with no external components connected directly to the actuator while gaining the feedback effect to counter the hysteresis and drifts errors of the actuator.

Pseudo-resistor structure, a closed-loop operational amplifier circuit and a bio-potential sensor
10811542 · 2020-10-20 · ·

A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.

PRECISION OPERATIONAL AMPLIFIER WITH A FLOATING INPUT STAGE

The operational amplifier disclosed includes an input stage configured to receive power from a floating supply in a low voltage range that can float according to the common mode voltage at the input. The floating supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage includes a first gain stage including field effect transistors and a second gain stage using bipolar transistors. The gain stages can be implemented differently to accommodate different applications and fabrication capabilities.

Semiconductor integrated circuit, reception device, memory system, and semiconductor storage device for reducing power consumption of equalizer
11989442 · 2024-05-21 · ·

A semiconductor integrated circuit has a reception circuit configured to receive a strobe signal of which a logic is intermittently switched in synchronization with a data signal, an output circuit configured to extract a low frequency component including at least a DC component of the strobe signal received by the reception circuit and to output a first signal, and a comparison circuit configured to compare a signal level of the first signal with a threshold level. The reception circuit is configured to change a boost amount of a high frequency component different from the low frequency component of the strobe signal based on a comparison result obtained by the comparison circuit.

PSEUDO-RESISTOR STRUCTURE, A CLOSED-LOOP OPERATIONAL AMPLIFIER CIRCUIT AND A BIO-POTENTIAL SENSOR
20190131462 · 2019-05-02 ·

A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.

Two-Stage Circuit With Power Supply Rejection Filter
20240275348 · 2024-08-15 ·

A two-stage circuit includes a differential-to-single-ended first stage with a differential pair of transistors. The first stage includes a current mirror including a diode-connected transistor having an RC circuit coupled to a drain of the diode-connected transistor. The current mirror is configured to mirror a power supply noise current conducted by the RC circuit through a first stage output terminal to a gate of an output transistor in a second stage of the two-stage circuit.

Systems and methods providing an intermodulation distortion sink

A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.