A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.

A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.

A buffer circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a load terminal. The control terminal is coupled to a preamplifier input terminal. The second transistor includes a first current terminal and a second current terminal. The first current terminal of the second transistor is coupled to the second current terminal of the first transistor. The third transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the third transistor is coupled to the load terminal. The second current terminal of the third transistor is coupled to a ground terminal. The control terminal of the third transistor is coupled to second current terminal of the second transistor.

A circuit includes a first transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to an output terminal, and the control terminal coupled to an input terminal, a second transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the second current terminal of the first transistor, a third transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the output terminal, and the control terminal coupled to the second current terminal of the second transistor, and a fourth transistor having a first current terminal and a control terminal, the first current terminal coupled to the second current terminal of the second transistor, and the control terminal coupled to the second current terminal of the third transistor.

A self-biasing output booster amplifier having an input amplifier stage, an output amplifier stage being operatively connected to an output of the input amplifier stage, and first and second current copying circuits. The second current copying circuit is biased from an output of the self-biasing output booster amplifier. The first and second current copying circuits are configured to copy at least a portion of the current through the output amplifier stage. The sum of the output of the second current copying circuit and the output of the output amplifier stage provides the output current of the self-biasing output booster amplifier, Finally, the input amplifier stage is biased from the output of the second current copying.

A self-biasing output booster amplifier having an input amplifier stage, an output amplifier stage being operatively connected to an output of the input amplifier stage, and first and second current copying circuits. The second current copying circuit is biased from an output of the self-biasing output booster amplifier. The first and second current copying circuits are configured to copy at least a portion of the current through the output amplifier stage. The sum of the output of the second current copying circuit and the output of the output amplifier stage provides the output current of the self-biasing output booster amplifier, Finally, the input amplifier stage is biased from the output of the second current copying.

A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.