A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

A bandgap reference circuit including a clamp circuit is provided. The bandgap reference circuit performs the calibration only for one time in a normal mode to store a control code of a reference generator of the clamp circuit. In a suspend mode, the control code is used for controlling the reference generator to cause the clamp circuit to provide a desired source voltage, and a bandgap reference voltage source is shut down to reduce the power consumption.

A bandgap reference circuit including a clamp circuit is provided. The bandgap reference circuit performs the calibration only for one time in a normal mode to store a control code of a reference generator of the clamp circuit. In a suspend mode, the control code is used for controlling the reference generator to cause the clamp circuit to provide a desired source voltage, and a bandgap reference voltage source is shut down to reduce the power consumption.

A variable attenuator (v-ATT) is disclosed. The v-ATT includes an input terminal, an output terminal, a transmission line between the input and output terminals, at least two stages provided between the transmission line and the ground, and a bias unit. Each of the stages includes a field effect transistor (FET) that varies impedance between the transmission line and the ground according to a bias provided to the gate thereof. The bias unit generates the biases each provided to the stages. One of the features of the v-ATT is that at least one of the stages receives at least one of the biases that is different from biases provided to other of the at least one of the stages.

Voltage regulator circuitry includes a first gain stage, a second gain stage, and a feedback stage. Feedback is provided between the feedback stage, the second gain stage, and the first gain stage in order to tightly regulate an output voltage of the voltage regulator circuitry such that the output voltage is independent of process variations present in the devices therein. The voltage regulator circuitry is fabricated using a pseudomorphic high electron mobility transistor (pHEMT) process in order to reduce the size thereof and provide short turn-on times and low quiescent current.

Voltage regulator circuitry includes a first gain stage, a second gain stage, and a feedback stage. Feedback is provided between the feedback stage, the second gain stage, and the first gain stage in order to tightly regulate an output voltage of the voltage regulator circuitry such that the output voltage is independent of process variations present in the devices therein. The voltage regulator circuitry is fabricated using a pseudomorphic high electron mobility transistor (pHEMT) process in order to reduce the size thereof and provide short turn-on times and low quiescent current.

A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

The disclosure relates to a current converter circuit. Example embodiments include a current converter circuit (600) for converting a linear input current (Ictrl_lin) to an exponential output current (Ictrl_sum), the current converter circuit (600) comprising first and second current converters (601, 602), each of which comprises: an input current branch (603.sub.1, 603.sub.2) with an input current source (604.sub.1, 604.sub.2) connected in series with a tuning voltage circuit (605.sub.1, 605.sub.2) and a tuning resistor (606.sub.1, 606.sub.2) between a supply voltage line (607) and a common voltage line (608); and an output current branch (609.sub.1, 609.sub.2) with an output transistor (610.sub.1, 610.sub.2) having a collector connected to an output node (611.sub.1, 611.sub.2), a emitter connected to the common voltage line (608) and a base connected to the tuning voltage circuit (605.sub.1, 605.sub.2), wherein the output nodes (611.sub.1, 611.sub.2) of the first and second current converters (601, 602) are connected to a summing output node (612) of the current converter circuit (600)