Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

A radio frequency (RF) generator includes a RF power source configured to output an RF power signal, and a controller coupled to the RF power source. The controller is configured to generate a pulse to modulate the RF power signal of the RF power source. The pulse includes one or more state transitions. The controller is further configured to receive a sync signal indicative of one or more operating characteristics or parameters of another RF generator, and adjust at least one of the state transitions of the pulse to synchronize the state transition with a defined phase of the received sync signal. Other example RF generators, RF power delivery systems including one or more RF generators, and control methods for adjusting a state transition of a pulse to synchronize the state transition with a defined phase of a sync signal are also disclosed.

A radio frequency (RF) generator includes a RF power source configured to output an RF power signal, and a controller coupled to the RF power source. The controller is configured to generate a pulse to modulate the RF power signal of the RF power source. The pulse includes one or more state transitions. The controller is further configured to receive a sync signal indicative of one or more operating characteristics or parameters of another RF generator, and adjust at least one of the state transitions of the pulse to synchronize the state transition with a defined phase of the received sync signal. Other example RF generators, RF power delivery systems including one or more RF generators, and control methods for adjusting a state transition of a pulse to synchronize the state transition with a defined phase of a sync signal are also disclosed.

An output stage of an Ethernet transmitter is provided. The output stage is coupled to a resistor and includes a first output terminal, a second output terminal, a first transistor, and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source, a first drain, and a first gate, the first source being coupled to a first reference voltage and the first drain being coupled to the second output terminal. The first transistor group is coupled to the first reference voltage and the first output terminal. The first transistor group includes multiple transistors which are connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on.

An output stage of an Ethernet transmitter is provided. The output stage is coupled to a resistor and includes a first output terminal, a second output terminal, a first transistor, and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source, a first drain, and a first gate, the first source being coupled to a first reference voltage and the first drain being coupled to the second output terminal. The first transistor group is coupled to the first reference voltage and the first output terminal. The first transistor group includes multiple transistors which are connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on.

A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.

A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.