Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

A temperature-compensated low-pass filter includes a differential amplifier that controls a first transistor to pass a subthreshold current through the transistor to charge a capacitor with low-pass-filtered output voltage. A second transistor has a first terminal coupled to an input terminal of the low-pass filter and has a second terminal coupled to a current source conducting a bias current. The differential amplifier also controls the second transistor to conduct the bias current responsive to a difference between a complementary-to-absolute-temperature reference voltage and a voltage of the second terminal of the second transistor.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

In an embodiment a low-pass filter arrangement has an input terminal for receiving an input voltage, a first voltage source coupled to the input terminal, a serial connection comprising a first and a second filter diode, the serial connection being coupled to the first voltage source, wherein a connection point between the first and the second filter diode is coupled to an output terminal of the filter arrangement, and a first filter capacitor coupled between the output terminal and a filter reference potential terminal. Therein the first voltage source is adapted to provide a first adjustable forward voltage whereby the first and the second filter diodes are both biased in a forward direction.

In an embodiment a low-pass filter arrangement has an input terminal for receiving an input voltage, a first voltage source coupled to the input terminal, a serial connection comprising a first and a second filter diode, the serial connection being coupled to the first voltage source, wherein a connection point between the first and the second filter diode is coupled to an output terminal of the filter arrangement, and a first filter capacitor coupled between the output terminal and a filter reference potential terminal. Therein the first voltage source is adapted to provide a first adjustable forward voltage whereby the first and the second filter diodes are both biased in a forward direction.

Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).