Disclosed is a method and a battery management system for estimating the parameters of an equivalent circuit model for a battery. The equivalent circuit model includes a first resistor, a second resistor connected in series to the first resistor and a capacitor connected in parallel to the second resistor. The method according to an embodiment of the present disclosure individually estimates the resistance of the first resistor and the resistance of the second resistor based on a first number of terminal voltages and a first number of currents measured in a sequential order at each time step in a sliding time window having a predefined size, and stores data indicating the estimated results in the memory.

A system identification device for performing fast real-time identification for a system from input/output data includes a filter robust to disturbance, by setting the maximum energy gain from the disturbance to a filter error, as an evaluation criterion, smaller than a given upper limit. The filter estimates a state estimation value of a state of the system.

Disclosed is a method and a battery management system for estimating the parameters of an equivalent circuit model for a battery. The equivalent circuit model includes a first resistor, a second resistor connected in series to the first resistor and a capacitor connected in parallel to the second resistor. The method according to an embodiment of the present disclosure individually estimates the resistance of the first resistor and the resistance of the second resistor based on a first number of terminal voltages and a first number of currents measured in a sequential order at each time step in a sliding time window having a predefined size, and stores data indicating the estimated results in the memory.

A system identification device for performing fast real-time identification for a system from input/output data includes a filter robust to disturbance, by setting the maximum energy gain from the disturbance to a filter error, as an evaluation criterion, smaller than a given upper limit. The filter estimates a state estimation value of a state of the system.

The present disclosure provides a permanent-magnet fault-tolerant in-wheel motor based on an active sensorless strategy and drive and design methods thereof. The present disclosure proposes the permanent-magnet fault-tolerant in-wheel motor drive system based on an active sensorless strategy by considering sensorless operation performance in advance in a motor design stage. The present disclosure adopts fractional-slot concentrated windings, and ingeniously arranges alternating poles, a multi-layer magnetic barrier, and auxiliary permanent magnets, thus improving a sensorless operation accuracy of the motor while ensuring fault tolerance of the motor. The present disclosure proposes a frequency-band-adaptive secondary harmonic suppression strategy at a control layer to suppress an influence of a secondary salient harmonic on position observation and improve dynamic response performance of a system.

The present disclosure provides a permanent-magnet fault-tolerant in-wheel motor based on an active sensorless strategy and drive and design methods thereof. The present disclosure proposes the permanent-magnet fault-tolerant in-wheel motor drive system based on an active sensorless strategy by considering sensorless operation performance in advance in a motor design stage. The present disclosure adopts fractional-slot concentrated windings, and ingeniously arranges alternating poles, a multi-layer magnetic barrier, and auxiliary permanent magnets, thus improving a sensorless operation accuracy of the motor while ensuring fault tolerance of the motor. The present disclosure proposes a frequency-band-adaptive secondary harmonic suppression strategy at a control layer to suppress an influence of a secondary salient harmonic on position observation and improve dynamic response performance of a system.

Various implementations described herein are directed to a device having a write circuit that provides data for storage. The device may include a memory circuit that stores the data in leaky bitcells with capacitive elements that gradually discharge over a pre-determined period of time. The device may include a read circuit that enables the leaky bitcells to operate as one or more memory storage elements. The device may include a query circuit that identifies matches between a query data and output data provided by the read circuit.